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2308B-2DCI 参数 Datasheet PDF下载

2308B-2DCI图片预览
型号: 2308B-2DCI
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, SOIC-16]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 13 页 / 166 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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IDT2308B
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308B, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay
adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs.
Ensure the outputs are loaded equally, for zero output-output skew.
REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS
1500
1000
REF to CLKA/CLKB Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)
4