IDT2308A
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS - INDUSTRIAL
Symbol
t
1
t
1
t
1
Parameter
Output Frequency
Output Frequency
Output Frequency
Duty Cycle = t
2
÷
t
1
(-1, -2, -3, -4, -1H, -2H)
Duty Cycle = t
2
÷
t
1
(-1, -2, -3, -4, -1H, -2H)
t
3
t
3
t
3
t
4
t
4
t
4
t
5
Rise Time (-1, -2, -3, -4)
Rise Time (-1, -2, -3, -4)
Rise Time (-1H, -2H)
Fall Time (-1, -2, -3, -4)
Fall Time (-1, -2, -3, -4)
Fall Time (-1H)
Output to Output Skew on same Bank
(-1, -2, -3, -4)
Output to Output Skew (-1H, -2H)
Output Bank A to Output Bank B (-1, -4, -2H)
Output Bank A to Output Bank B Skew (-2, -3)
t
6
t
7
t
8
t
J
Delay, REF Rising Edge to FBK Rising Edge
Device to Device Skew
Output Slew Rate
Cycle to Cycle Jitter
(-1, -1H, -4)
tJ
Conditions
30pF Load, all devices
20pF Load, -1H, -2H Devices
15pF Load, -1, -2, -3, -4 devices
Measured at 1.4V, F
OUT
= 66.66MHz
30pF Load
Measured at 1.4V, F
OUT
= 50MHz
15pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 15pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 30pF Load
Measured between 0.8V and 2V, 15pF Load
Measured between 0.8V and 2V, 30pF Load
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
All outputs equally loaded
Measured at V
DD
/2
Measured at V
DD
/2 on the FBK pins of devices
Measured between 0.8V and 2V on -1H, -2H
device using Test Circuit 2
Measured at 66.67 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 133.3 MHz, loaded outputs, 15pF Load
Measured at 66.67 MHz, loaded outputs, 30pF Load
Measured at 66.67 MHz, loaded outputs, 15pF Load
Stable Power Supply, valid clocks presented
on REF and FBK pins
Min.
10
10
10
40
45
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
1
⎯
⎯
⎯
⎯
⎯
⎯
Typ.
⎯
⎯
⎯
50
50
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
0
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
Max.
100
133.3
133.3
60
55
2.2
1.5
1.5
2.2
1.5
1.25
200
200
200
400
±250
700
⎯
200
200
100
400
400
1
Unit
MHz
MHz
MHz
%
%
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
ps
ps
V/ns
ps
ps
ms
Cycle to Cycle Jitter
(-2, -2H, -3)
PLL Lock Time
t
LOCK
7
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
