IDT2305
3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TYPICAL DUTY CYCLE
(1)
AND I
DD
TRENDS
(2)
FOR IDT2305-1
Duty Cycle vs V
DD
(for 30pf loads over frequency - 3.3V, 25C)
60
58
56
Duty Cycle (% )
Duty Cycle (% )
Du ty Cycle vs V
D D
(for 10pF load s over frequency - 3.3V, 25C)
60
58
56
54
52
50
48
46
44
42
40
33M Hz
66M Hz
100M Hz
133M Hz
54
52
50
48
46
44
42
40
3
3.1
3.2
3.3
3.4
3.5
3.6
33M H z
66M H z
100M Hz
3
3.1
3.2
3.3
3.4
3.5
3.6
V
DD
(V)
Duty Cycle vs Frequency
(for 30pf loads over temperature - 3.3V)
60
58
56
Duty Cycle (% )
V
DD
(V)
Du ty C ycle vs Fre qu ency
(for 10pF loads over tem perature - 3.3V)
60
58
56
Duty Cycle (% )
54
52
50
48
46
44
42
40
20
40
60
80
100
120
140
-40C
0C
25C
70C
85C
54
52
50
48
46
44
42
40
20
40
60
80
100
120
140
-40C
0C
25C
70C
85C
Frequency (MHz)
I
DD
vs Number of Loaded Outputs
(for 30pf loads over frequency - 3.3V, 25C)
140
120
100
80
60
140
120
100
80
60
Frequency (M Hz)
I
D D
vs Num ber of Loade d O utputs
(for 10pF loads over frequency - 3.3V, 25C)
I
DD
(m A)
33M H z
66M H z
100M Hz
I
DD
(mA)
33M H z
66M Hz
100M Hz
40
20
0
0
2
4
6
8
40
20
0
0
2
4
6
8
Number of Loaded Outputs
Number of Loaded O utputs
NOTES:
1. Duty Cycle is taken from typical chip measured at 1.4V.
2. I
DD
data is calculated from I
DD
= I
CORE
+ nCVf, where I
CORE
is the unloaded current. (n = Number of outputs; C = Capacitance load per output (F);
V = Supply Voltage (V); f = Frequency (Hz))
8
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
