ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Block Diagram
100Base-T
10/100 MII/RMII
MAC
Interface
Interface
MUX
PCS
• Framer
• CRS/COL
Detection
• Parallel to Serial
• 4B/5B
PMA
• Clock Recovery
• Link Monitor
• Signal Detection
• Error Detection
TP_PMD
• MLT-3
• Stream Cipher
• Adaptive Equalizer
• Baseline Wander
Correction
Integrated
Switch
10Base-T
MII
Extended
Register
Set
Low-Jitter
Clock
Synthesizer
Clock
Smart Power
Control
Block
Power
Twisted-
Pair
Interface to
Magnetics
Modules and
RJ45
Connector
MII
Management
Interface
Configuration
and Status
Auto-
Negotiation
LEDs and PHY
Address
Pin Assignment
P1/ISO/LED1
P0/LED0
P4/LED2
P4/LED2
P1/LED1
P0/LED0
REFOUT
REFIN
REFIN
REFOUT
AMDIX
AMDIX
1
1
31
31
VDDD
TXD3
TXD2
TXD1
LED3
VDDD
TXD0
TXD0
TXD3
TXD2
TXD1
LED3
TP_AP
TP_AP
TP_AN
VSS
NLG40 Without Ground Connecting to
TXEN
TXEN
TP_AN
VSS
SPEED/TXCLK
NOD/RXER
NLG40 Without Ground
Pad
Thermal
Connecting to
Thermal Pad
TXER
NOD/RXER
SPEED/TXCLK
VDD
TP_BN
ANSEL/RXCLK
VDD
ANSEL/RXCLK
TXER
SPEED
TP_BN
TP_BP
TP_BP
VDD
VDD
TCSR
TCSR
VSS
VSS
SPEED
RMII/RXDV
RMII/RXDV
FDPX/RXD0
11
21
FDPX/RXD0
SI/LED4
SI/LED4
11
21
HWSW/CRS
MDC
REGPIN/COL
AMDIXRXD3
REGPIN/COL
HWSW/CRS
40-pin MLF
40-pin MLF
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
RXTR1RXD1
AMDIXRXD3
RESET_N
P3/RXD2
RXTR1RXD1
RESET_N
P2/INT
MDIO
P2/INT
MDIO
MDC
VDDIO
P3/RXD2
VDDIO
2
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
