ICS1894-40
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
PHYCEIVER
Power Management
The ICS1894-40 supports a Deep Power Mode (DPD) that
is enabled under the following conditions:
1. The Phy is not Receiving any signal from the partner (Link
Down)
2. The MAC is not transmitting data to the Phy (TXEN Low)
Once the above conditions are met, the Phy goes into DPD
mode after 32s (typical).
The logic internal to the device can be selectively shut down
in DPD mode depending on Register 24 Bits 8-4.
Block Diagram of the Different Sections of the PHY as Affected by Register 24 bits
Reference Clock
TPLL
Controlled by Register 24.7
10/100M Drive Clock
TX_STRUCTURE
XMIT_DAC
Controlled
by Register
24.5
RX and
Equalizer
Controlled by
Register 24.6
OUT
IN
If XMIT_DAC is
powered down,
this block is
High_Z
CDR
Controlled by
Register 24.4
Bias for 10/100M
Vbg
Bias for Rx
BGAP
Bias Current
Clock Reference Interface
The REFIN pin provides the ICS1894-40 Clock Reference
Interface. The ICS1894-40 requires a single clock reference
with a frequency of 25 MHz 50 parts per million. This
accuracy is necessary to meet the interface requirements of
the ISO/IEEE 8802-3 standard, specifically clauses 22.2.2.1
and 24.2.3.4. The ICS1894-40 supports two clock source
configurations: a CMOS oscillator or a CMOS driver. The
input to REFIN is CMOS (10% to 90% VDD), not TTL.
Alternately, a 25MHz crystal may be used.
IDT® 10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE
12
ICS1894-40
REV G 060110
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
