ICS1893BF Data Sheet - Release
Chapter 8 Pin Diagram, Listings, and Descriptions
Table 8-7. MAC Interface Pins: Media Independent Interface (MII) (Continued)
Pin
Pin
Pin
Pin Description
Name Number
Type
MDIO
26
Input/ Management Data Input/Output.
Output The signal on this pin can be tri-stated and can be driven by one of the
following:
• A Station Management Entity (STA), to transfer command and data
information to the registers of the ICS1893BF.
• The ICS1893BF, to transfer status information.
All transfers and sampling are synchronous with the signal on the MDC
pin.
Note: If the ICS1893BF is to be used in an application that uses the
mechanical MII specification, MDIO must have a 1.5 kΩ ±5%
pull-up resistor at the ICS1893BF end and a 2 kΩ ±5% pull-down
resistor at the station management end. (These resistors enable
the station management to determine if the connection is intact.)
RXCLK
34
Output Receive Clock.
The ICS1893BF sources the RXCLK to the MAC interface. The
ICS1893BF uses RXCLK to synchronize the signals on the following pins:
RXD[3:0], RXDV, and RXER. The following table contrasts the behavior
on the RXCLK pin when the mode for the ICS1893BF is either 10Base-T
or 100Base-TX.
10Base-T
100Base-TX
The RXCLK frequency is 2.5
MHz.
The RXCLK frequency is 25 MHz.
The ICS1893BF generates its
The ICS1893BF generates its
RXCLK from the MDI data stream RXCLK from the MDI data stream
using a digital PLL. When the MDI while there is a valid link (that is,
data stream terminates, the PLL
continues to operate,
synchronously referenced to the
last packet received.
either data or IDLEs). In the
absence of a link, the ICS1893BF
uses the REF_IN clock to
generate the RXCLK.
The ICS1893BF switches
While the ICS1893BF is bringing
between clock sources during the up a link, a clock phase change of
period between when its CRS is
asserted and prior to its RXDV
being asserted. While the
ICS1893BF is locking onto the
incoming data stream, a clock
phase change of up to 360
degrees can occur.
up to 360 degrees can occur.
The RXCLK aligns once per
packet.
The RXCLK aligns once, when
the link is being established.
Note: The signal on the RXCLK pin is conditioned by the RXTRI pin.
ICS1893BF, Rev. E, 8/11/09
August, 2009
Copyright © 2009, IDT, Inc.
All rights reserved.
98
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