ICS1893BF Data Sheet Rev. E - Release
Chapter 5 Interface Overviews
5.2 Serial Management Interface
The ICS1893BF provides an ISO/IEC compliant, two-wire Serial Management Interface as part of its MAC
Interface. This Serial Management Interface is used to exchange control, status, and configuration
information between a Station Management entity (STA) and the physical layer device (PHY), that is, the
ICS1893BF.
The ISO/IEC standard also specifies a frame structure and protocol for this interface as well as a set of
Management Registers that provide the STA with access to a PHY such as the ICS1893BF. A Serial
Management Interface is comprised of two signals: a bi-directional data pin (MDIO) along with an
associated input pin for a clock (MDC). The clock is used to synchronize all data transfers between the
ICS1893BF and the STA.
In addition to the ISO/IEC defined registers, the ICS1893BF provides several extended status and control
registers to provide more refined control of the MII and MDI interfaces. For example, the QuickPoll Detailed
Status Register provides the ability to acquire the most-important status functions with a single MDIO read.
Note: In the ICS1893BF, the MDIO and MDC pins remain active for all the MAC Interface modes (that is,
10M MII, 100M MII, 100M Symbol, and 10M Serial).
5.3 Twisted-Pair Interface
For the twisted-pair interface, the ICS1893BF uses 1:1 ratio transformers for both transmit and receive.
Better operation results from using a split ground plane through the transformer. In this case:
• The RJ-45 transformer windings must be on the chassis ground plane along with the Bob Smith
termination.
• The ICS1893BF system ground plane must include the ICS1893BF-side transformer windings along with
the 61.9Ω resistors and the 120-nH inductor.
• The transformer provides the isolation with one set of windings on one ground plane and another set of
windings on the second ground plane.
5.3.1 Twisted-Pair Transmitter
The twisted-pair transmitter driver uses an H-bridge configuration. IDT transformer requirements:
• Turns Ratio 1:1
• Chokes may be used on chip or cable side or both sides
• No power connections to the transformer. Transformer power is supplied by the ICS1893BF
• MIDCOM 7090-37 or equivalent symetrical magnetics are used
Figure 5-1 shows the design for the ICS1893BF twisted-pair interface.
• Two 61.9Ω1% resistors are in series, with a 120-nH 5% inductor between them. These components form
a network that connects across both pairs of twisted pairs A and B.
• The center taps on the chip side are each bypassed to VSS with a 0.1uf capacitor. Do not connect the
chip side center taps together (use separate bypass capacitors). The ICS1893BF biases the selected
transmit pair and receive pair differently based on assigned function.
• Both twisted pairs A and B have an assigned plus and minus.
Note:
1. Keep all TX traces as short as possible.
2. When longer board twisted pair traces are used, 50Ω-characteristic board trace impedance is
desirable.
ICS1893BF, Rev. E, 8/11/09
August, 2009
Copyright © 2009, IDT, Inc.
All rights reserved.
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