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    1893BFLF 参数 Datasheet PDF下载

    1893BFLF图片预览
    型号： 1893BFLF
    PDF下载： 下载PDF文件 查看货源
    内容描述： 3.3 -V的10Base -T / 100BASE - TX集成PHYceiverâ ?? ¢ [3.3-V 10Base-T/100Base-TX Integrated PHYceiver™]
    分类和应用： 网络接口电信集成电路电信电路光电二极管PC
    文件页数/大小： 136 页 / 1040 K
    品牌： IDT [ INTEGRATED DEVICE TECHNOLOGY ]
     浏览型号1893BFLF的Datasheet PDF文件第1页浏览型号1893BFLF的Datasheet PDF文件第2页浏览型号1893BFLF的Datasheet PDF文件第3页浏览型号1893BFLF的Datasheet PDF文件第5页浏览型号1893BFLF的Datasheet PDF文件第6页浏览型号1893BFLF的Datasheet PDF文件第7页浏览型号1893BFLF的Datasheet PDF文件第8页浏览型号1893BFLF的Datasheet PDF文件第9页  
    ICS1893AF Data Sheet - Release
    Table of Contents
    Table of Contents
    Section
    Chapter 8
    8.1
    8.1.1
    8.1.2
    8.1.3
    8.1.4
    8.2
    8.2.1
    8.2.2
    8.2.3
    8.2.4
    8.2.5
    8.2.6
    8.2.7
    8.2.8
    8.2.9
    8.2.10
    8.3
    8.3.1
    8.3.2
    8.3.3
    8.3.4
    8.3.5
    8.3.6
    8.3.7
    8.3.8
    8.3.9
    8.3.10
    8.3.11
    8.3.12
    8.3.13
    8.4
    Title
    Page
    Management Register Set ............................................................................................... 55
    Introduction to Management Register Set .............................................................56
    Management Register Set Outline .........................................................................56
    Management Register Bit Access ..........................................................................57
    Management Register Bit Default Values ..............................................................57
    Management Register Bit Special Functions .........................................................58
    Register 0: Control Register ...................................................................................59
    Reset (bit 0.15) ......................................................................................................59
    Loopback Enable (bit 0.14) ....................................................................................60
    Data Rate Select (bit 0.13) .....................................................................................60
    Auto-Negotiation Enable (bit 0.12) .........................................................................60
    Low Power Mode (bit 0.11) ....................................................................................61
    Isolate (bit 0.10) .....................................................................................................61
    Restart Auto-Negotiation (bit 0.9) ..........................................................................61
    Duplex Mode (bit 0.8) .............................................................................................62
    Collision Test (bit 0.7) ............................................................................................62
    IEEE Reserved Bits (bits 0.6:0) .............................................................................62
    Register 1: Status Register ....................................................................................63
    100Base-T4 (bit 1.15) ............................................................................................63
    100Base-TX Full Duplex (bit 1.14) .........................................................................64
    100Base-TX Half Duplex (bit 1.13) ........................................................................64
    10Base-T Full Duplex (bit 1.12) .............................................................................64
    10Base-T Half Duplex (bit 1.11) .............................................................................64
    IEEE Reserved Bits (bits 1.10:7) ...........................................................................65
    MF Preamble Suppression (bit 1.6) .......................................................................65
    Auto-Negotiation Complete (bit 1.5) .......................................................................65
    Remote Fault (bit 1.4) ............................................................................................66
    Auto-Negotiation Ability (bit 1.3) ............................................................................66
    Link Status (bit 1.2) ................................................................................................67
    Jabber Detect (bit 1.1) ...........................................................................................67
    Extended Capability (bit 1.0) ..................................................................................67
    Register 2: PHY Identifier Register ........................................................................68
    ICS1893AF, Rev D 10/26/04
    Copyright © 2004, Integrated Circuit Systems, Inc.
    All rights reserved.
    4
    October, 2004

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