ICS1893AF Data Sheet - Release
Chapter 8 Management Register Set
8.14 Register 19: Extended Control Register 2
The Extended Control Register provides more refined control of the internal ICS1893AF operations.
Note:
1. For an explanation of acronyms used in Table 8-20, see Chapter 1, “Abbreviations and Acronyms”.
2. During any write operation to any bit in this register, the STA must write the default value to all
Reserved bits.
Table 8-21. Extended Control Register (register [0x13])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
SF
De-
Hex
cess
fault
19.15 Node/Repeater Mode
Node mode
Repeater mode
Software mode
RO
RO
–
–
0†
1†
4
19.14 Hardware/Software
Mode
Hardware mode
19.13 Remote Fault
No faults detected
Remote fault
detected
RO
–
0
19.12 ICS reserved
19.11 ICS reserved
19.10 ICS reserved
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
RW
RW
RO
RW
RW
RW
–
–
–
–
–
–
0
0
0
0
0
0
0
0
19.9
19.8
19.7
ICS reserved
ICS reserved
Twisted Pair Tri-State
Enable, TPTRI
Twisted Pair Signals Twisted Pair Signals
are not Tri-Stated or
No effect
are Tri-Stated
19.6
19.5
19.4
19.3
19.2
19.1
19.0
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
ICS reserved
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
Read unspecified
RW
RW
RW
RW
RW
RW
RW
–
–
–
–
–
–
–
0
0
0
0
0
0
1
1
Automatic 100Base-TX
Power Down
Do not automatically Power down
power down automatically
† The default is the state of this pin at reset.
ICS1893AF, Rev D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
96
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
