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1893CF 参数 Datasheet PDF下载

1893CF图片预览
型号: 1893CF
PDF下载: 下载PDF文件 查看货源
内容描述: [Interface Circuit, 1-Trnsvr, CMOS, PDSO48, 0.300 MM INCH, SSOP-48]
分类和应用: 网络接口电信集成电路电信电路光电二极管
文件页数/大小: 136 页 / 1040 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1893AF Data Sheet - Release  
Chapter 7 Functional Blocks  
7.6 Functional Block: Management Interface  
As part of the MAC/Repeater Interface, the ICS1893AF provides a two-wire serial management interface  
which complies with the ISO/IEC 8802-3 standard MII Serial Management Interface. This interface is used  
to exchange control, status, and configuration information between a Station Management entity (STA) and  
the physical layer device (PHY). The PHY and STA exchange this data through a pre-defined set of  
management registers. The ISO/IEC standard specifies the following components of this serial  
management interface:  
A set of registers (Section 7.6.1, “Management Register Set Summary”)  
The frame structure (Section 7.6.2, “Management Frame Structure”)  
The protocol  
In compliance with the ISO/IEC specification, the ICS1893AF implementation of the serial management  
interface provides a bi-directional data pin (MDIO) along with a clock (MDC) for synchronizing the  
exchange of data. These pins remain active in all ICS1893AF MAC/Repeater Interface modes (that is, the  
10/100 MII, 100M Symbol, and 10M Serial interface modes).  
7.6.1 Management Register Set Summary  
The ICS1893AF implements a Management Register set that adheres to the ISO/IEC standard. This  
register set (discussed in detail in Chapter 8, “Management Register Set”) includes the mandatory ‘Basic’  
Control and Status registers and the ISO/IEC ‘Extended’ registers as well as some ICS-specific registers.  
7.6.2 Management Frame Structure  
The Serial Management Interface is a synchronous, bi-directional, two-wire, serial interface for the  
exchange of configuration, control, and status data between a PHY, such as an ICS1893AF, and an STA.  
All data transferred on an MDIO signal is synchronized by its MDC signal. The PHY and STA exchange  
data through a pre-defined register set.  
The ICS1893AF complies with the ISO/IEC defined Management Frame Structure and protocol. This  
structure supports both read and write operations. Table 7-2 summarizes the Management Frame  
Structure.  
Note: The Management Frame Structure starts from and returns to an IDLE condition. However, the IDLE  
periods are not part of the Management Frame Structure.  
Table 7-2. Management Frame Structure Summary  
Frame Field  
Frame Function  
Data  
Comment  
Acronym  
PRE  
Preamble (Bit 1.6)  
Start of Frame  
Operation Code  
PHY Address (Bits 16.10:6)  
Register Address  
Turnaround  
11..11  
01  
32 ones  
2 bits  
SFD  
OP  
10/01 (read/write) 2 bits  
PHYAD  
REGAD  
TA  
AAAAA  
RRRRR  
5 bits  
5 bits  
Z0/10 (read/write) 2 bits  
DDD..DD 16 bits  
DATA  
Data  
ICS1893AF
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
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