ICS1893AF Data Sheet - Release
Chapter 10 DC and AC Operating Conditions
10.5 Timing Diagrams
10.5.1 Timing for Clock Reference In (REF_IN) Pin
Table 10-8 lists the significant time periods for signals on the clock reference in (REF_IN) pin. Figure 10-2
shows the timing diagram for the time periods.
Note: The REF_IN switching point is 50% of VDD.
Table 10-8. REF_IN Timing
Time
Parameter
Conditions
Min.
Typ. Max. Units
Period
t1
t2
REF_IN Duty Cycle
REF_IN Period
–
–
40
–
50
40
60
–
%
ns
Figure 10-2. REF_IN Timing Diagram
t1
REF_IN
t2
ICS1893AF, Rev D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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