ICS1893AF Data Sheet - Release
Chapter 8 Management Register Set
8.11.7 Invalid Error Code Test (bit 16.2)
The Invalid Error Code Test bit allows an STA to force the ICS1893AF to transmit symbols that are typically
classified as invalid. The purpose of this test bit is to permit thorough testing of the 4B/5B encoding and the
serial transmit data stream by allowing generation of bit patterns that are considered invalid by the ISO/IEC
4B/5B definition.
When this bit is logic:
• Zero, the ISO/IEC defined 4B/5B translation takes place.
• One – and the TXER signal is asserted by the MAC/repeater – the MII input nibbles are translated
according to Table 8-17.
Table 8-17. Invalid Error Code Translation Table
Symbol
Meaning
MII Input Translation
Nibble
V
V
Invalid Code
Invalid Code
Invalid Code
Invalid Code
Error
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
00000
00001
00010
00011
00100
00101
00110
00111
00000
01101
01100
10001
10000
11001
11000
11111
V
V
H
V
Invalid Code
Invalid Code
ESD
V
R
V
Invalid Code
ESD
T
V
Invalid Code
SSD
K
V
Invalid Code
Invalid Code
SSD
V (S)
J
I
Idle
8.11.8 ICS Reserved (bit 16.1)
See Section 8.11.2, “ICS Reserved (bits 16.14:11)”, the text for which also applies here.
8.11.9 Stream Cipher Disable (bit 16.0)
The Stream Cipher Disable bit allows an STA to control whether the ICS1893AF employs the Stream
Cipher Scrambler in the transmit and receive data paths. When this bit is set to logic:
• Zero, the Stream Cipher Encoder and Decoder are both enabled for normal operations.
• One, the Stream Cipher Encoder and Decoder are disabled. This action results in an unscrambled data
stream (for example, the ICS1893AF transmits unscrambled IDLES, and so forth.
Note: The Stream Cipher Scrambler can be used only for 100-MHz operations.
ICS1893AF, Rev D 10/26/04
October, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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IDT [ INTEGRATED DEVICE TECHNOLOGY ]
