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1892Y-14 参数 Datasheet PDF下载

1892Y-14图片预览
型号: 1892Y-14
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 148 页 / 1762 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
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ICS1892  
10Base-T/100Base-TX Integrated PHYceiver™  
TSD  
8.11 Register 16: Extended Control Register  
Table 8-16 lists the bits for the Extended Control Register, which the ICS1892 provides to allow an STA to  
customize the operations of the device.  
Note:  
1. For an explanation of acronyms used in Table 8-16, see Chapter 1, “Abbreviations and Acronyms”.  
2. During any write operation to any bit in this register, the STA must write the default value to all  
Reserved bits.  
Table 8-16. Extended Control Register (register 16 [0x10])  
Bit  
Definition  
When Bit = 0  
When Bit = 1  
Ac-  
SF  
De-  
Hex  
cess  
fault  
16.15 Command Override Write Disabled  
enable  
Enabled  
RW  
SC  
0
16.14 ICS reserved  
16.13 ICS reserved  
16.12 ICS reserved  
16.11 ICS reserved  
16.10 PHY Address Bit 4  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
Read unspecified  
RW/0  
RW/0  
RW/0  
RW/0  
RO  
0
Read unspecified  
Read unspecified  
Read unspecified  
0
0
0
For a detailed explanation of this bit’s operation,  
see Section 6.9, “Status Interface”.  
P4RD†  
16.9  
16.8  
16.7  
16.6  
PHY Address Bit 3  
PHY Address Bit 2  
PHY Address Bit 1  
PHY Address Bit 0  
For a detailed explanation of this bit’s operation,  
see Section 6.9, “Status Interface”.  
RO  
RO  
RO  
RO  
P3TD†  
P2LI†  
For a detailed explanation of this bit’s operation,  
see Section 6.9, “Status Interface”.  
For a detailed explanation of this bit’s operation,  
see Section 6.9, “Status Interface”.  
P1CL†  
P0AC†  
8
For a detailed explanation of this bit’s operation,  
see Section 6.9, “Status Interface”.  
16.5  
16.4  
16.3  
16.2  
16.1  
16.0  
Stream Cipher Test Mode Normal operation  
Test mode  
RW  
RW/0  
RW  
0
1
0
0
0
ICS reserved  
Read unspecified  
NRZ encoding  
Disabled  
Read unspecified  
NRZI encoding  
Enabled  
NRZ/NRZI encoding  
Transmit invalid codes  
ICS reserved  
RW  
Read unspecified  
Read unspecified  
RW/0  
RW  
Stream Cipher disable  
Stream Cipher enabled Stream Cipher disabled  
† The default is the state of this pin at reset.  
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™  
ICS1892  
86  
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