欢迎访问ic37.com |
会员登录 免费注册
发布采购

1892Y-14 参数 Datasheet PDF下载

1892Y-14图片预览
型号: 1892Y-14
PDF下载: 下载PDF文件 查看货源
内容描述: [Ethernet Transceiver, 1-Trnsvr, CMOS, PQFP64]
分类和应用: 以太网:16GBASE-T电信电信集成电路
文件页数/大小: 148 页 / 1762 K
品牌: IDT [ INTEGRATED DEVICE TECHNOLOGY ]
 浏览型号1892Y-14的Datasheet PDF文件第41页浏览型号1892Y-14的Datasheet PDF文件第42页浏览型号1892Y-14的Datasheet PDF文件第43页浏览型号1892Y-14的Datasheet PDF文件第44页浏览型号1892Y-14的Datasheet PDF文件第46页浏览型号1892Y-14的Datasheet PDF文件第47页浏览型号1892Y-14的Datasheet PDF文件第48页浏览型号1892Y-14的Datasheet PDF文件第49页  
ICS1892  
TSD  
10Base-T/100Base-TXIntegrated PHYceiver™  
7.3.6 4B/5B Encoding/Decoding  
The 4B/5B coding methodology maps each 4-bit nibble to a 5-bit symbol (also called a “code group”). There  
are 32 five-bit symbols, which include the following:  
Of the 32 five-bit symbols, 16 five-bit symbols are required to represent the 4-bit nibbles.  
The remaining 16 five-bit symbols are available for control functions. The IEEE Standard defines 6  
symbols for control, and the remaining 10 symbols of this grouping are invalid. The 6 control symbols  
include the following:  
– /H/ represents a Transmit Error  
– /I/ represents an IDLE  
– Two symbols represent the Start-of-Stream Delimiter (SSD): /J/ and /K/  
– Two symbols represent the End-of-Stream Delimiter (ESD): /T/ and /R/  
If the ICS1892 PCS receives:  
– One of the 10 undefined symbols, it sets the QuickPoll Detailed Status Register’s Invalid Symbol bit  
(bit 17.7) to logic one.  
– A Halt symbol, it sets the Halt Symbol Detected bit in the QuickPoll Detailed Status Register (bit 17.6)  
to logic one.  
Note: By an STA (1) setting the Extended Control Register’s Transmit Invalid Codes bit (bit 16.2) to logic  
one and (2) asserting the TXER signal, an STA can force the ICS1892 to transmit symbols that are  
typically classified as invalid. For more information, see Section 8.11.7, “Invalid Error Code Test (bit  
16.2)”.  
IDT™ / ICS™ 10Base-T/100Base-TX Integrated PHYceiver™  
ICS1892  
45  
 复制成功!