ICS1527 Data Sheet
Section 2 Pin Descriptions
Section 2
Pin Descriptions
Table 2-1
ICS1527
Pin Descriptions
PIN NO. PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSSD
SDA
SCL
VSYNC
EXTFB
HSYNC
VDDA
VSSA
I2CADR
LOCK
HSYNC_out
CLK
VDDQ
VSYNC_out
VSSQ
VDDD
TYPE
POWER
IN/OUT
IN
IN
IN
IN
POWER
POWER
IN
LVCMOS
OUT
LVCMOS
OUT
LVCMOS
OUT
POWER
LVCMOS
OUT
POWER
POWER
DESCRIPTION
Digital ground
Serial data
Serial clock
Vertical sync
External feedback
Horizontal sync
Analog supply
Analog ground
I
2
C device address
Lock
HSYNC output
Pixel clock output
Output driver supply
VSYNC output
Output driver ground
Digital supply
COMMENTS
I
2
C-bus
I
2
C-bus
From External Divider
Clock input to PLL
Power for analog circuitry
Ground for analog circuitry
Chip I
2
C address select
PLL lock
Schmitt-trigger filtered HSYNC
realigned with the output pixel clock
LVCMOS driver for full-speed clock
Power for output drivers
Schmitt-trigger filtered VSYNC
realigned with the output pixel clock
Ground for output drivers
Power for digital sections
Notes
1
1
1&2
1&2
1&2
Notes: 1. These LVTTL inputs are 5 V tolerant.
2. Connect to ground if unused.
MDS 1527 G
4
Revision 110905
w w w. i dt . c o m
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
