ICS1526
Video Clock Synthesizer
ICS1526 Data Sheet
Table 5-4
AC Characteristics
TSD
Section 5 AC/DC Operating Conditions
Parameter
Symbol
f
VCO
K
f
OSC
f
HSYNC
f
VSYNC
V
IH
V
IL
Min.
40
Typical
Max.
400
Units
MHz
MHz/V
Notes
General
VCO Frequency
VCO Gain
165
0.02
8
30
1.7
VSS - 0.3
0.2
V
IH
V
IL
2
VSS - 0.3
2
VSS - 0.3
100
10,000
120
5.5
1.1
0.8
5.5
0.8
VDD+0.3
0.8
0.4
6.0
AC Inputs
OSC Input Frequency
HSYNC Input Frequency
VSYNC Input Frequency
Input High Voltage
Input Low Voltage
Input Hysteresis
MHz
kHz
Hz
V
V
V
V
V
V
V
V
V
IOUT = 3 mA
Determined by
external Rset resistor
VDDD = 3.3 V
2
30 kHz input to 50
MHz output
HSYNC in to CLK out
1
Schmitt trigger active
Analog Input (HSYNC/VSYNC)
SDA, SCL, OSC Digital Inputs
Input High Voltage
Input Low Voltage
I
2
CADDR Digital
Input High Voltage
Input Low Voltage
Input
V
IH
V
IL
V
OL
V
OH
SDA Digital Output
SDA Output Low Voltage
SDA Output High Voltage
LVCMOS Outputs (CLK, HSYNC_out, VSYNC_out, LOCK)
Output Frequency
Duty Cycle
Jitter, STJ, RMS
Jitter, STJ, pk-pk
Jitter, Input-Output
HSYNC to HSYNC_out
propagation delay (without
Schmitt trigger)
HSYNC to HSYNC_out
propagation delay (with
Schmitt-trigger)
CLK to HSYNC_out/
VSYNC_out skew
Clock/ HSYNC_out/
VSYNC_out
Transition Time - Rise
T
CR
1.0
F
s
S
DC
STJ
STJ
IOJ
2.5
45
50
0.027
0.200
2.500
2
9
110
55
MHz
%
ns
ns
ns
ns
6
10
ns
1
1.0
1.5
ns
ns
2
MDS1526 K
9
Revision 110905
IDT™
In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1
/ ICS™
Video Clock Synthesizer
9
w w w. i c s t . c o m
ICS1526
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
