IDT1339
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
RTC
Table 4. Alarm Mask Bits
DY/DT
X
X
X
X
0
1
Alarm 1 Register Mask Bits (Bit 7)
A1M4
1
1
1
1
0
0
Alarm Rate
Alarm once per second.
Alarm when seconds match.
Alarm when minutes and seconds match.
Alarm when hours, minutes, and seconds match.
Alarm when date, hours, minutes, and seconds match.
Alarm when day, hours, minutes, and seconds match.
A1M3
1
1
1
0
0
0
A1M2
1
1
0
0
0
0
A1M1
1
0
0
0
0
0
DY/DT
X
X
X
0
1
Alarm 2 Register Mask Bits (Bit 7)
A2M4
1
1
1
0
0
Alarm Rate
Alarm once per minute (00 sec. of every min.).
Alarm when minutes match.
Alarm when hours and minutes match.
Alarm when date, hours, and minutes match.
Alarm when day, hours, and minutes match.
A2M3
1
1
0
0
0
A2M2
1
0
0
0
0
Special-Purpose Registers
The IDT1339 has two additional registers (control and status) that control the RTC, alarms, and square-wave output.
Control Register (0Eh)
Bit 7
EOSC
Bit 6
0
Bit 5
BBSQI
Bit 4
RS2
Bit 3
RS1
Bit 2
INTCN
Bit 1
A2IE
Bit 0
A1IE
Bit 7: Enable Oscillator (EOSC).
This bit when set to logic 0 starts the oscillator. When this bit is set to a logic 1,
the oscillator is stopped. This bit is enabled (logic 0) when power is first applied.
Bit 5: Battery-Backed Square-Wave and Interrupt Enable (BBSQI).
This bit when set to a logic 1 enables the
square wave or interrupt output when
V
CC
is absent and the IDT1339 is being powered by the V
BACKUP
pin. When
BBSQI is a logic 0, the SQW/INT pin goes high impedance when
V
CC
falls below the power-fail trip point. This bit is
disabled (logic 0) when power is first applied.
Bits 4 and 3: Rate Select (RS2 and RS1).
These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 5 shows the square-wave frequencies that can be selected with the RS bits.
These bits are both set to logic 1 (32 kHz) when power is first applied.
IDT®
REAL-TIME CLOCK WITH SERIAL I
2
C INTERFACE
8
IDT1339
REV K 032910
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
