IDT1338B-31
REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM
RTC
Note 7: Measured with a 32.768 kHz crystal on X1 and X2.
Note 8: After this period, the first clock pulse is generated.
Note 9: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of
IHMIN
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL
HD:DAT
LOW
signal.
Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t
> to 250 ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+
R(MAX)
t
= 1000 + 250 = 1250 ns before the SCL line is released.
SU:DAT
Note 12: C —total capacitance of one bus line in pF.
B
Note 13: Guaranteed by design. Not production tested.
Note 14: The parameter t
is the period of time the oscillator must be stopped for the OSF flag to be set over the
OSF
voltage range of 0.0V < VCC < VCCMAX and 1.3 V < V
< 3.7 V.
BACKUP
Timing Diagram
IDT™ REAL-TIME CLOCK WITH BATTERY BACKED NON-VOLATILE RAM 14
IDT1338B-31 REV A 112309
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
