IDT1337
REAL-TIME CLOCK WITH I2C SERIAL INTERFACE
RTC
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
32.768 kHz Clock Accuracy with
Internal Crystal
TA=25°C
VCC=3.3 V
±30
ppm
(crystal accuracy
±20ppm)
Note 1: Limits at -40°C are guaranteed by design and are not production tested.
Note 2: SCL only.
Note 3: SDA, INTA, and SQW/INTB.
Note 4: I
—SCL clocking at maximum frequency = 400 kHz, VIL = 0.0V, VIH = VCC.
CCA
2
Note 5: Specified with the I C bus inactive, VIL = 0.0V, VIH = VCC.
Note 6: SQW enabled.
Note 7: Specified with the SQW function disabled by setting INTCN = 1.
Note 8: Using recommended crystal on X1 and X2.
Note 9: The device is fully accessible when 1.8 < VCC < 5.5 V. Time and date are maintained when 1.3 V < VCC <
1.8 V.
Note 10: After this period, the first clock pulse is generated.
Note 11: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
of
IHMIN
the SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 12: The maximum t
need only be met if the device does not stretch the LOW period (t
) of the SCL
HD:DAT
LOW
signal.
Note 13: A fast-mode device can be used in a standard-mode system, but the requirement t
> to 250 ns must
SU:DAT
then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t
+
R(MAX)
t
= 1000 + 250 = 1250 ns before the SCL line is released.
SU:DAT
Note 14: C —total capacitance of one bus line in pF.
B
Note 15: Guaranteed by design. Not production tested.
2
IDT™ REAL-TIME CLOCK WITH I C SERIAL INTERFACE
14
IDT1337
REV H 120208
IDT [ INTEGRATED DEVICE TECHNOLOGY ]
