欢迎访问ic37.com |
会员登录 免费注册
发布采购

9250-50 参数 Datasheet PDF下载

9250-50图片预览
型号: 9250-50
PDF下载: 下载PDF文件 查看货源
内容描述: 频率发生器和缓冲器集成为PIII和图拉丁 [Frequency Generator & Integrated Buffers for PIII & Tualatin]
分类和应用:
文件页数/大小: 13 页 / 141 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号9250-50的Datasheet PDF文件第2页浏览型号9250-50的Datasheet PDF文件第3页浏览型号9250-50的Datasheet PDF文件第4页浏览型号9250-50的Datasheet PDF文件第5页浏览型号9250-50的Datasheet PDF文件第6页浏览型号9250-50的Datasheet PDF文件第7页浏览型号9250-50的Datasheet PDF文件第8页浏览型号9250-50的Datasheet PDF文件第9页  
Integrated
Circuit
Systems, Inc.
ICS9250-50
Frequency Generator & Integrated Buffers for PIII & Tualatin™
Recommended Application:
815B Solano B step style chipset
Output Features:
2 - CPUs @ 2.5V, up to 133MHz.
13 - SDRAM @ 3.3V, up to 133MHz.
3 - 3V66 @ 3.3V, 2x PCI MHz.
8 - PCI @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
1 - REF @ 3.3V, 14.318MHz.
1 - IOAPIC @ 2.5V 16.67MHz.
Features:
Support PC133 SDRAM.
Up to 133MHz frequency support
Support power management through PD#
Spread spectrum for EMI control
(± 0.25% Center Spread or 0 to -0.5% down spread)
Uses external 14.318MHz crystal
FS pins for frequency select
Key Specifications:
CPU Output Jitter: <250ps
CPU Output Skew: <175ps
PCI Output Skew: <500ps
3V66 Output Skew <175ps
For group skew timing, please refer to the
Group Timing Relationship Table.
Pin Configuration
VDDA
X1
X2
GNDA
GND3V66
3V66-0
3V66-1
3V66-2
VDD3V66
VDDPCI
1
*FS0/PCICLK0
1
*FS1/PCICLK1
1
*SEL24_48#/PCICLK2
GNDPCI
PCICLK3
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
Vtt_PWRGD/PD#
SCLK
SDATA
VDDSDR
SDRAM11
SDRAM10
GNDSDR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FS4*
VDDLAPIC
IOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
GNDLCPU
GNDSDR
SDRAM0
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
SDRAM5
GNDSDR
SDRAM6
SDRAM7
SDRAM_F
VDDSDR
GND48
1
24_48MHz/FS2 *
1
48MHz/FS3*
VDD48
VDDSDR
SDRAM8
SDRAM9
GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength.
* 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
Functionality
FS4 FS3 FS2 FS1 FS0 CPU SDRAM
0
0
0
0
0
66.67 100.00
0
1
0
0
0 100.00 100.00
1
0
0
0
0 133.33 133.33
1
1
0
0
0 133.33 100.00
3V66
66.67
66.67
66.67
66.67
PCI
33.33
33.33
33.33
33.33
REF0
For other hardware/I
2
C selectable frequencies please
refer to Byte 0 frequency select register.
CPU
DIVDER
2
CPUCLK (1:0)
SDRAM
DIVDER
12
SDRAM (11:0)
SDRAM_F
FS(4:0)
PD#
Vtt_PWRGD
SEL24_48#
SDATA
SCLK
Control
Logic
Config.
Reg.
IOAPIC
DIVDER
Power Groups
VDD48 = Fixed PLL power
GND48 = Fixed PLL GND
VDDA = Power for CPU PLL
GNDA = GND for CPU PLL
IOAPIC
PCI
DIVDER
8
PCICLK (7:0)
3V66
DIVDER
3
3V66 (2:0)
0594A—07/08/02
ICS9250-50