MK1491-14
OPTi ACPI Firestar Clock Source
Pin Assignment
Table #1. F1, F2 Frequency
Select (MHz)
Table #2. Host/PCI Frequency Select (MHz)
STOP#
F1(SEL0)
VDD
VDD
28
27
26
25
24
1
2
3
4
5
6
7
8
9
SEL1 SEL0
F1
F2
FS1
FS0
HOST PCI (S/A=0) PCI (S/A=1)
X14I
0
0
1
1
0
1
0
1
14.318
14.318
24.000
16.934
14.318
48.000
14.318
24.576
0
0
66.66
60
33.33*
33.33*
33.33*
33.33*
HOST/2
HOST/2
HOST/2
HOST/2
X14O
0
1
F2(PS)
GND
14.3(HS)
HOST1
1
1
0
1
75
PCI(FS1)
50
23 GND
22 PCIF(LE)
21 PCI(SEL1)
HOST2
*2 MHz Accuracy
VDD
HOST1-4
HOST3
20
19
Low EMI for HOST & PCI
VDD
Table #3. Host 5-7 Skew Control
PCI(S/A)
HOST4 10
VDD
HS
LE
Low EMI
HOST5-7
18 PCI(FS0)
17 GND
16 SLOW#
GND
11
12
2.5V
3.3V
0
0
OFF
HOST5
1
1
ON
EHOST6 13
HOST5-7
15
HOST7
VDD
14
Table #4. Power Down Control (IDD measured at 3.3V)
IDD typ.
50 mA
32 mA
44 mA
1 µA
STOP# SLOW#
STATE
HOST
PCI DESCRIPTION
1
1
0
0
1
0
0
1
ON
ON
ON All Clocks On.
SLOW
CLK OFF
33 MHz ON Host Clock smooth frequency transition to and from 33.33 MHz.
LOW Asynchronously clamp HOST5, 7 to GND. HOST1-4,6, PCIF, F1, F2, 14.3M, continue to run.
LOW All outputs asynchronously clamped low. PLLs and 14.3 MHz oscillators are off.
*
PLL/OSC OFF LOW
*PCI Function Select (PS) set at Power Up. PS=0, PCI=LOW; PS=1, PCI=ON when clock is switched to “CLK OFF” mode.
Pin Descriptions
Pin #
Name
Type Description
1, 20, 26
VDD
X14I
P
I
Connect to +3.3V. Must be same voltage on all pins.
Crystal connection. Connect to a 14.31818 MHz crystal or input clock.
2
3
X14O
GND
O
P
Crystal connection. Connect to a 14.31818 MHz crystal, or leave unconnected for clock.
Connect to Ground.
4, 11, 17, 23
5
6, 7, 9, 10
8
14.3(HS)
HOST 1, 2, 3, 4
VDD HOST1-4
HOST 5
EHOST 6
VDD HOST5-7
HOST7
I/O 14.318 MHz output. Amplitude matches VDD. Skew input control for Host 5-7.
O
P
Host Output clocks 1, 2, 3 and 4. Amplitude matches VDDHOST1-4
Connect to VDD supply.
12
13
14
15
O
O
P
O
I
Host Output clock 5. Amplitude matches VDD
Early Host Output clock 6. Amplitude matches VDD
Connect to 2.5 V or 3.3 V. Host 5-7 skew adjusted with HS input. See Table #3 above.
Host Output clock 7. Amplitude matches VDD
Controls clock frequency and power downs, as defined in Table #4 above.
.
HOST5-7
.
HOST5-7
.
HOST5-7
16
SLOW#
18
19
21
22
24
25
27
28
PCI(FS0)
PCI(S/A)
PCI(SEL1)
PCIF(LE)
PCI(FS1)
F2(PS)
I/O PCI Output clock, CPU Frequency Select input, as per Table #2 above. Amplitude = VDD.
I/O PCI Output clock, and Asynchronous PCI Select input, as per Table #2 above.
I/O PCI Output clock, and Frequency Select 1 input, as per Table #1 above.
I/O PCI Output clock that stays enabled when other PCI clocks are low. Low EMI enable input.
I/O PCI output and Frequency Select input. See Table #2 above.
I/O Fixed frequency output and PCI Function Select for "CLK OFF" mode.
I/O Fixed frequency output and frequency SEL0 input per Table #1 above.
F1(SEL0)
STOP#
I
Controls clock frequency and power downs, as defined in Table #4 above.
Key: I = Input, O = Output, P = Power supply connection, I/O = Input on power up, becomes an Output after 10ms.
Internal pull-ups are on pins 5, 16, 18, 19, 21, 22, 24, 25, 27, 28.
MDS 1491-14 B
2
Revision 061801
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