Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
Type
Power
Input
Unused
Power
Input
Input
Pullup
Pullup
Description
Analog supply pin.
Feedback clock input. LVCMOS / LVTTL interface levels.
No connect.
Power supply ground.
Non-inver ting LVPECL differential clock input.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2
3, 4, 5, 6
7, 13, 17,
21, 25, 29
8
9
Nam e
V
DDA
FB_CLK
nc
GND
PCLK
nPCLK
Pullup/ Inver ting LVPECL differential clock input.
Pulldown Internally biased to V
DDO
/2.
Active HIGH Master Reset. Active LOW output enable. When
logic High, the internal dividers are reset and the outputs are
10
MR/nOE
Input
Pulldown
tri-stated (HiZ). When logic LOW, the internal dividers and
the outputs are enabled. LVCMOS / LVTTL interface levels.
Power
Output supply pins.
11, 15, 19, 23, 27
V
DDO
12, 14, 16, 18,
Q7, Q6, Q5, Q4,
Clock outputs. LVCMOS / LVTTL interface levels.
Output
20, 22, 24, 26
Q3, Q2, Q1, Q0
14
Ω
typical output impedance.
Feedback clock output. LVCMOS / LVTTL interface levels.
28
QFB
Output
14
Ω
typical output impedance.
Selects VCO when HIGH. When LOW, selects PCLK,
30
PLL_SEL
Input
Pullup
nPCLK. LVCMOS / LVTTL interface levels.
31
nBYPASS
Input
Pullup
Selects PLL when HIGH. When LOW, in Bypass mode.
Selects VCO ÷2 when HIGH. Selects VCO ÷1 when LOW.
32
VCO_SEL
Input
Pullup
LVCMOS / LVTTL interface levels.
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
R
PULLUP
R
PULLDOWN
C
P D
R
OUT
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Power Dissipation Capacitance (per output)
Output Impedance
V
DDA
, V
DDO
= 3.465V
5
Test Conditions
Minimum Typical
4
51
51
7
14
12
Maximum
Units
pF
KΩ
KΩ
pF
Ω
T
ABLE
3A. O
UTPUT
C
ONTROL
P
IN
F
UNCTION
T
ABLE
Input
MR/nOE
1
0
Outputs
QFB, Q0:Q7
HiZ
Enabled
T
ABLE
3B. P
ROGRAMMABLE
O
UTPUT
F
REQUENCY
F
UNCTION
T
ABLE
Inputs
Bypass
0
1
1
1
1
86953BYI-147
PLL_SEL
X
0
0
1
1
VCO_SEL
X
0
1
0
1
Operation
Test Mode: PLL and divider bypass
Test Mode: PLL bypass
Test Mode: PLL bypass
PLL Mode
PLL Mode
Outputs
QFB, Q0:Q7
CLK
CLK/4
CLK/8
VCO/4
VCO/8
REV. B APRIL 23, 2004
www.icst.com/products/hiperclocks.html
2
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