PRELIMINARY INFORMATION
ICS525-07/08
LVCMOS User Configurable Clock
AC Electrical Characteristics
Unless stated otherwise, VDD = 1.8 V to 2.5 V
Parameter
Symbol
Conditions
Min.
5
Typ.
Max. Units
Crystal input
27
50
MHz
MHz
MHz
MHz
ns
Input Frequency
F
IN
Clock input
-40 to +85°C
-40 to +85°C
20% to 80%
80% to 20%
at VDD/2
2
Output Frequency (ICS525-07)
Output Frequency (ICS525-08)
Output Clock Rise Time
F
F
10
0.4
200
200
OUT
OUT
1
1
Output Clock Fall Time
ns
Output Clock Duty Cycle
45
49 to 51
55
50
%
Power-down Time, PD low to
clocks stopped
ns
ms
ps
ps
ps
ps
Power-up Time, PD high to
clocks stable
5
Absolute Clock Period Jitter,
VDD = 2.5 V
t
Deviation from mean
One Sigma
ja
One Sigma Clock Period Jitter,
VDD = 2.5 V
t
js
ja
Absolute Clock Period Jitter,
VDD = 1.8 V
t
Deviation from mean
One Sigma
One Sigma Clock Period Jitter,
VDD = 1.8 V
t
js
NOTE 1: Phase relationship between input and output can change at power-up.
MDS 525-07/08 A
7
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
