ICS1893BY-10 Data Sheet - Release
Chapter 7 Management Register Set
7.13.7 SQE Test Inhibit (bit 18.2)
The SQE Test Inhibit bit allows an STA to prevent the generation of the Signal Quality Error pulse. When an
STA sets this bit to logic:
• Zero, the ICS1893BY-10 enables its SQE Test generation.
• One, the ICS1893BY-10 disables its SQE Test generation.
The SQE Test provides the ability to verify that the Collision Logic is active and functional. A 10Base-T SQE
test is performed by pulsing the Collision signal for a short time after each packet transmission completes,
that is, after TXEN goes inactive.
Note:
1. The SQE Test is automatically inhibited in full-duplex and repeater modes, thereby disabling the
functionality of this bit.
2. This bit is a control bit and not a status bit. Therefore, it is not updated to indicate this automatic
inhibiting of the SQE test in full-duplex mode or repeater mode.
7.13.8 Link Loss Inhibit (bit 18.1)
The Link Loss Inhibit bit allows an STA to prevent the ICS1893BY-10 from dropping the link in 10Base-T
mode. When an STA sets this bit to logic:
• Zero, the state machine behaves normally and the link status is based on the signaling detected Twisted-
Pair Receiver inputs.
• One, the ICS1893BY-10 10Base-T Link Integrity Test state machine is forced into the ‘Link Passed’ state
regardless of the Twisted-Pair Receiver input conditions.
7.13.9 Squelch Inhibit (bit 18.0)
The Squelch Inhibit bit allows an STA to control the ICS1893BY-10 Squelch Detection in 10Base-T mode.
When an STA sets this bit to logic:
• One, before the ICS1893BY-10 can establish a valid link, the ICS1893BY-10 must receive valid
10Base-T data.
• Zero, before the ICS1893BY-10 can establish a valid link, the ICS1893BY-10 must receive both valid
10Base-T data followed by an IDL.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
