ICS1893BY-10 Data Sheet - Release
Chapter 7 Management Register Set
7.5.3 Revision Number (bits 3.3:0)
Table 7-10 lists the valid ICS1893BY-10 revision numbers, which are 4-bit binary numbers stored in bits
3.3:0.
Table 7-10. ICS1893BY-10 Revision Number
Decimal
Bits 3.3:0
Description
ICS 1893B Release with Auto-MDIX
2
0010
7.6 Register 4: Auto-Negotiation Register
Table 7-11 lists the bits for the Auto-Negotiation Register. An STA uses this register to select the
ICS1893BY-10 capabilities that it wants to advertise to its remote link partner. During the auto-negotiation
process, the ICS1893BY-10 advertises (that is, exchanges) capability data with its remote link partner by
using a pre-defined Link Code Word. The Link Code Word is embedded in the Fast Link Pulses exchanged
between PHYs when the ICS1893BY-10 has its Auto-Negotiation sublayer enabled. The value of the Link
Control Word is established based on the value of the bits in this register.
Note: For an explanation of acronyms used in Table 7-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 7-11. Auto-Negotiation Advertisement Register (register 4 [0x04])
Bit
Definition
When Bit = 0
When Bit = 1
Ac-
cess
SF De- Hex
fault
4.15 Next Page
Next page not supported
Always 0
Next page supported
N/A
R/W
CW
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0†
0
0
1
E
1
4.14 IEEE reserved
4.13 Remote fault
4.12 IEEE reserved
4.11 IEEE reserved
4.10 IEEE reserved
4.9 100Base-T4
Locally, no faults detected
Always 0
Local fault detected
N/A
R/W
CW
0†
0†
0†
0
Always 0
N/A
CW
Always 0
N/A
CW
Always 0. (Not supported.)
N/A
CW
4.8 100Base-TX, full duplex Do not advertise ability
4.7 100Base-TX, half duplex Do not advertise ability
Advertise ability
Advertise ability
Advertise ability
Advertise ability
Note 1
Note 1
Note 1
Note 1
CW
1
1
4.6 10Base-T, full duplex
4.5 10Base-T half duplex
4.4 Selector Field bit S4
4.3 Selector Field bit S3
4.2 Selector Field bit S2
4.1 Selector Field bit S1
4.0 Selector Field bit S0
Do not advertise ability
Do not advertise ability
1
1
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
IEEE 802.3-specified default N/A
0
CW
0
CW
0
CW
0
N/A
IEEE 802.3-specified
default
CW
1
† As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
Note 1:
• In Hardware mode (that is, HW/SW pin is logic zero), this bit is a Read-Only bit.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
72
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
