ICS1893BY-10 Data Sheet - Release
Chapter 7 Management Register Set
7.2 Register 0: Control Register
Table 7-5 lists the bits for the Control Register, a 16-bit register used to establish the basic operating modes
of the ICS1893BY-10.
• The Control Register is accessible through the MII Management Interface.
• Its operation is independent of the MAC/Repeater Interface configuration.
• It is fully compliant with the ISO/IEC Control Register definition.
Note: For an explanation of acronyms used in Table 7-5, see Chapter 1, “Abbreviations and Acronyms”.
Table 7-5. Control Register (Register 0 [0x00]
Bit
Definition
When Bit = 0
No effect
When Bit = 1
Ac-
cess
SF
De- Hex
fault
0.15 Reset
ICS1893BY-10 enters
Reset mode
R/W
SC
0
3
0.14 Loopback enable
0.13 Data rate select
Disable Loopback mode Enable Loopback mode
10 Mbps operation 100 Mbps operation
R/W
R/W
R/W
R/W
R/W
–
–
–
–
–
0
1
0.12 Auto-Negotiation enable DisableAuto-Negotiation Enable Auto-Negotiation
1
0.11 Low-power mode
0.10 Isolate
Normal power mode
No effect
Low-power mode
0
0/4†
Isolate ICS1893BY-10
from MII
0/1†
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
Auto-Negotiation restart No effect
Restart Auto-Negotiation
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
SC
–
0
Duplex mode
Collision test
Half-duplex operation
No effect
Full-duplex operation
0
Enable collision test
–
0
0
0
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
IEEE reserved
Always 0
N/A
N/A
N/A
N/A
N/A
N/A
N/A
–
0‡
0‡
0‡
0‡
0‡
0‡
0‡
Always 0
–
Always 0
–
Always 0
–
Always 0
–
Always 0
–
Always 0
–
† Whenever the PHY address of Table 7-16:
• Is equal to 00000 (binary), the Isolate bit 0.10 is logic one.
• Is not equal to 00000, the Isolate bit 0.10 is logic zero.
‡ As per the IEEE Std 802.3u, during any write operation to any bit in this register, the STA must write the default value
to all Reserved bits.
7.2.1 Reset (bit 0.15)
This bit controls the software reset function. Setting this bit to logic one initiates an ICS1893BY-10 software
reset during which all Management Registers are set to their default values and all internal state machines
are set to their idle state. For a detailed description of the software reset process, see Section 4.1.2.3,
“Software Reset”.
During reset, the ICS1893BY-10 leaves bit 0.15 set to logic one and isolates all STA management register
accesses. However, the reset process is not complete until bit 0.15 (a Self-Clearing bit), is set to logic zero,
which indicates the reset process is terminated.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
60
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
