欢迎访问ic37.com |
会员登录 免费注册
发布采购

ICS1893BYI-10LF 参数 Datasheet PDF下载

ICS1893BYI-10LF图片预览
型号: ICS1893BYI-10LF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用:
文件页数/大小: 143 页 / 1665 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
 浏览型号ICS1893BYI-10LF的Datasheet PDF文件第51页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第52页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第53页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第54页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第56页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第57页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第58页浏览型号ICS1893BYI-10LF的Datasheet PDF文件第59页  
ICS1893BY-10 - Release  
Chapter 6 Functional Blocks  
6.6.2.7 Management Frame Turnaround  
A valid management frame includes a turn-around field (TA), which is a 2-bit time space between the  
REGAD field and the Data field. This time allows an ICS1893BY-10 and an STA to avoid contentions during  
read transactions. During an operation that is a:  
Read, an ICS1893BY-10 remains in the high-impedance state during the first bit time and subsequently  
drives its MDIO pin to logic zero for the second bit time.  
Write, an ICS1893BY-10 waits while the STA transmits a logic one, followed by a logic zero on its MDIO  
pin.  
6.6.2.8 Management Frame Data  
A valid management frame includes a 16-bit Data field for exchanging the register contents between the  
ICS1893BY-10 and the STA. All Management Registers are 16 bits wide, matching the width of the Data  
field. During a transaction that is a:  
Read, (OP is 10b) the ICS1893BY-10 obtains the contents of the register identified in the REGAD field  
and returns this Data to the STA synchronously with its MDC signal.  
Write, (OP is 01b) the ICS1893BY-10 stores the value of the Data field in the register identified in the  
REGAD field.  
If the STA attempts to:  
Read from a non-existent ICS1893BY-10 register, the ICS1893BY-10 returns logic one for all bits in the  
Data field, FFFFh.  
Write to a non-existant ICS1893BY-10 register, the ICS1893BY-10 isolates the Data field of the  
management frame from every reaching the registers.  
Note: The first Data bit transmitted and received is the most-significant bit of a Management Register, bit  
X.15.  
6.6.2.9 Serial Management Interface Idle State  
The MDIO signal is in an idle state during the time between STA transactions. When the Serial  
Management Interface is in the idle state, the ICS1893BY-10 disables (that is, tri-states) its MDIO pin,  
which enters a high-impedance state. The ISO/IEC 8802-3 standard requires that an MDIO signal be idle  
for at least one bit time between management transactions. However, the ICS1893BY-10 does not have  
this limitation and can support a continual bit stream on its MDIO signals.  
ICS1893BY-10 Rev A 3/24/04  
March, 2004  
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
55  
 复制成功!