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ICS1893BYI-10LF 参数 Datasheet PDF下载

ICS1893BYI-10LF图片预览
型号: ICS1893BYI-10LF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用:
文件页数/大小: 143 页 / 1665 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1893BY-10 - Release  
Chapter 6 Functional Blocks  
6.5.3 10Base-T Operation: Clock Recovery  
The ICS1893BY-10 recovers its receive clock from the Manchester-encoded data stream obtained from its  
Twisted-Pair Receiver using a phase-locked loop (PLL). The ICS1893BY-10 then uses this recovered clock  
for synchronizing data transmission between itself and the MAC/repeater. Receive-clock PLL acquisitions  
begin with reception of the MAC Frame Preamble and continue as long as the ICS1893BY-10 is receiving  
data.  
6.5.4 10Base-T Operation: Idle  
An ICS1893BY-10 transmits Normal Link Pulses (that is, 10Base-T Idles) on its MDI in the absence of data  
(that is, when the MAC/repeater is not requiring it to transmit any data). During this time the link is Idle, and the  
ICS1893BY-10 periodically transmits link pulses at a rate of one link pulse every 16 ms in compliance with the  
ISO/IEC 8802-3 standard. In 10Base-T mode, the ICS1893BY-10 continues transmitting link pulses even  
while receiving data. This situation does not generate a Collision Detect signal (COL) because link pulses  
indicate an idle state for a link.  
6.5.5 10Base-T Operation: Link Monitor  
When an ICS1893BY-10 is in 10Base-T mode, its Link Monitor Function observes the data received by the  
10Base-T Twisted-Pair Receiver to determine the link status. The results of this continual monitoring are  
stored in the Link Status bit. The Station Management entity (STA) can access the Link Status bit in either  
the Status Register (bit 1.2) or the QuickPoll Detailed Status Register (bit 17.0).  
When the Link Status bit is:  
Zero, either a valid link is not established or the link is momentarily dropped since either the last read of  
the Link Status bit or the last reset of the ICS1893BY-10.  
One, a valid link is established.  
The ICS1893BY-10 Link Status bit is a latching low (LL) bit. (For more information on latching high and  
latching low bits, see Section 7.1.4.1, “Latching High Bits” and Section 7.1.4.2, “Latching Low Bits”.)  
The criteria used by the Link Monitor Function to declare a link either valid (that is, ‘established’ or ‘up’) or  
invalid (that is, ‘failed’ or ‘down’) depends upon these factors: the present state of the link, whether its  
Smart Squelch function is enabled, and the incoming data.  
When the 10Base-T link is:  
Invalid, and the Smart Squelch function is:  
– Disabled (bit 18.0 is logic 1), the Link Monitor Function must detect at least one of the following  
events before transitioning its link from the invalid state to the valid state:  
• More than seven, ISO/IEC-defined, Normal Link Pulses (NLPs)  
• Any valid data  
– Enabled (bit 18.0 is logic 0), the Link Monitor Function must detect at least one of the following  
events before transitioning its link from the invalid state to the valid state:  
• More than seven, ISO/IEC-defined, Normal Link Pulses (NLPs)  
• Any valid data followed by a valid IDL  
Valid, and the Smart Squelch function is:  
– Disabled (bit 18.0 is logic 1), the Link Monitor Function continues to report its link as valid as long as  
it continues to detect any of the following:  
• ISO/IEC-defined, Normal Link Pulses (NLPs)  
• Any valid data  
ICS1893BY-10 Rev A 3/24/04  
March, 2004  
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
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