ICS1893BY-10 - Release
Chapter 6 Functional Blocks
6.3.2 PMA Sublayer
The ICS1893BY-10 100Base-X PMA Sublayer consists of two interfaces: one to the Physical Coding
sublayer and the other to the Physical Medium Dependent sublayer. Functionally, the PMA sublayer is
responsible for the following:
• Link Monitoring
• Carrier Detection
• NRZI encoding/decoding
• Transmit Clock Synthesis
• Receive Clock Recovery
6.3.3 PCS/PMA Transmit Modules
Both the PCS and PMA sublayers have Transmit modules.
6.3.3.1 PCS Transmit Module
The ICS1893BY-10 PCS Transmit module accepts nibbles from the MAC/Repeater Interface and converts
the nibbles into 5-bit ‘code groups’ (referred to here as ‘symbols’). In addition, the PCS Transmit module
performs a parallel-to-serial conversion on the symbols, and subsequently passes the resulting serial bit
stream to the PMA sublayer.
The first 16 nibbles of each MAC/Repeater Frame represent the Frame Preamble. The PCS replaces the
first two nibbles of the Frame Preamble with the Start-of-Stream Delimiter (SSD), that is, the symbols /J/K/.
After receipt of the last Frame nibble, detected when TX_EN = FALSE, the PCS appends to the end of the
Frame an End-of-Stream Delimiter (ESD), that is, the symbols /T/R/. (The ICS1893BY-10 PCS does not
alter any other data included within the Frame.)
The PCS Transmit module also performs collision detection. In compliance with the ISO/IEC specification,
when the transmission and reception of data occur simultaneously and the ICS1893BY-10 is in:
• Half-duplex mode, the ICS1893BY-10 asserts the collision detection signal (COL).
• Full-duplex mode, COL is always FALSE.
6.3.3.2 PMA Transmit Module
The ICS1893BY-10 PMA Transmit module accepts a serial bit stream from its PCS and converts the data
into NRZI format. Subsequently, the PMA passes the NRZI bit stream to the Twisted-Pair Physical Medium
Dependent (TP-PMD) sublayer.
The ICS1893BY-10 PMA Transmit module uses a digital PLL to synthesize a transmit clock from the Clock
Reference Interface. When the ICS1893BY-10 is configured for an interface that is:
• 10M MII (that is, 10Base-T), the TXCLK signal is 2.5 MHz
• 10M Serial Interface, the TXCLK signal is 10 MHz
• Either of the following, the TXCLK signal (a buffered version of the REF_IN signal) is 25 MHz:
– 100M MII (that is, 100Base-TX)
– 100M Symbol Interface
Note:
1. All of the TXCLK signals are derived from the REF_IN signal that goes to the digital PLL.
2. For the MII, for both the 10Base-T and 100Base-TX modes, the clock that is generated synchronizes
all data transfers across the MII.
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
