ICS1893BY-10 Data Sheet - Release
Table of Contents
Table of Contents
Section
Title
Page
Chapter 7
7.1
Management Register Set ............................................................................................... 56
Introduction to Management Register Set .............................................................57
7.1.1
7.1.2
7.1.3
7.1.4
Management Register Set Outline .........................................................................57
Management Register Bit Access ..........................................................................58
Management Register Bit Default Values ..............................................................58
Management Register Bit Special Functions .........................................................59
7.2
Register 0: Control Register ...................................................................................60
Reset (bit 0.15) ......................................................................................................60
Loopback Enable (bit 0.14) ....................................................................................61
Data Rate Select (bit 0.13) .....................................................................................61
Auto-Negotiation Enable (bit 0.12) .........................................................................61
Low Power Mode (bit 0.11) ....................................................................................62
Isolate (bit 0.10) ......................................................................................................62
Restart Auto-Negotiation (bit 0.9) ..........................................................................62
Duplex Mode (bit 0.8) .............................................................................................63
Collision Test (bit 0.7) ............................................................................................63
IEEE Reserved Bits (bits 0.6:0) .............................................................................63
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.2.7
7.2.8
7.2.9
7.2.10
7.3
Register 1: Status Register ....................................................................................64
100Base-T4 (bit 1.15) ............................................................................................64
100Base-TX Full Duplex (bit 1.14) .........................................................................65
100Base-TX Half Duplex (bit 1.13) ........................................................................65
10Base-T Full Duplex (bit 1.12) .............................................................................65
10Base-T Half Duplex (bit 1.11) .............................................................................65
IEEE Reserved Bits (bits 1.10:7) ...........................................................................66
MF Preamble Suppression (bit 1.6) .......................................................................66
Auto-Negotiation Complete (bit 1.5) .......................................................................66
Remote Fault (bit 1.4) ............................................................................................67
Auto-Negotiation Ability (bit 1.3) ............................................................................67
Link Status (bit 1.2) ................................................................................................67
Jabber Detect (bit 1.1) ...........................................................................................68
Extended Capability (bit 1.0) ..................................................................................68
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.4
Register 2: PHY Identifier Register ........................................................................69
ICS1893BY-10 Rev A 3/24/04
March, 2004
Copyright © 2004, Integrated Circuit Systems, Inc.
All rights reserved.
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ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
