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ICS1893BYI-10LF 参数 Datasheet PDF下载

ICS1893BYI-10LF图片预览
型号: ICS1893BYI-10LF
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3 -V的10Base -T / 100BASE - TX集成PHYceiver [3.3-V 10Base-T/100Base-TX Integrated PHYceiver]
分类和应用:
文件页数/大小: 143 页 / 1665 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1893BY-10 - Release  
Chapter 8 Pin Diagram, Listings, and Descriptions  
Table 8-3. PHY Address and LED Pins  
Pin  
Pin  
Pin  
Pin Description  
Name Number  
Type  
P3TD 62  
Input or PHY (Address Bit) 3 / Transmit Data LED.  
Output For more information on this pin, see Section 5.8, “Status Interface”.  
These multi-function configuration pins are:  
– Input pins during either a power-on reset or a hardware reset. In this  
case, these pins configure the address of the ICS1893BY-10 when it  
is in either hardware mode or software mode.  
– Output pins following reset. In this case, this pin provides link status  
for the ICS1893BY-10.  
As an input pin:  
This pin establishes the address for the ICS1893BY-10. When the  
signal on one of these pins is logic:  
– Low, that address bit is set to logic zero.  
– High, that address bit is set to logic one.  
As an output pin:  
When the signal on this pin is:  
– De-asserted, this state indicates the ICS1893BY-10 does not have  
Transmit activity.  
– Asserted, this state indicates the ICS1893BY-10 has Transmit  
Activity.  
Caution: This pin must not float. (See the notes at Section 8.3.2,  
“Multi-Function (Multiplexed) Pins: PHY Address and LED  
Pins”.)  
P4RD  
64  
Input or PHY (Address Bit) 4 / Receive Data LED.  
Output For more information on this pin, see Section 5.8, “Status Interface”.  
This multi-function configuration pin is:  
– An input pin during either a power-on reset or a hardware reset. In  
this case, this pin configures the ICS1893BY-10 when it is in either  
hardware mode or software mode.  
– An output pin following reset. In this case, the pin provides activity  
status of the ICS1893BY-10.  
As an input pin:  
This pin establishes the address for the ICS1893BY-10. When the  
signal on this pin is logic:  
– Low, that address bit is set to logic zero.  
– High, that address bit is set to logic one.  
As an output pin:  
When the signal on this pin is:  
– De-asserted, this state indicates the ICS1893BY-10 does not have  
Receive activity.  
– Asserted, this state indicates the ICS1893BY-10 has Receive activity.  
Caution: This pin must not float. (See the notes at Section 8.3.2,  
“Multi-Function (Multiplexed) Pins: PHY Address and LED  
Pins”.)  
ICS1893BY-10 Rev A 3/24/04  
March, 2004  
Copyright © 2004, Integrated Circuit Systems, Inc.  
All rights reserved.  
103  
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