ICS1893BF Data Sheet - Release
Table of Contents
Table of Contents
Section
7.1.2
7.1.3
7.2.3
7.2.8
7.2.9
7.2.10
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10
7.3.11
7.3.12
7.3.13
7.4
Title
Page
Management Register Bit Access .......................................................................... 51
Management Register Bit Default Values .............................................................. 51
Data Rate Select (bit 0.13) ..................................................................................... 54
Duplex Mode (bit 0.8) ............................................................................................. 56
Collision Test (bit 0.7) ............................................................................................ 56
IEEE Reserved Bits (bits 0.6:0) ............................................................................. 56
Register 1: Status Register .................................................................................... 57
100Base-T4 (bit 1.15) ............................................................................................ 57
100Base-TX Full Duplex (bit 1.14) ......................................................................... 58
100Base-TX Half Duplex (bit 1.13) ........................................................................ 58
10Base-T Full Duplex (bit 1.12) ............................................................................. 58
10Base-T Half Duplex (bit 1.11) ............................................................................ 58
IEEE Reserved Bits (bits 1.10:7) ........................................................................... 59
MF Preamble Suppression (bit 1.6) ....................................................................... 59
Auto-Negotiation Complete (bit 1.5) ....................................................................... 59
Remote Fault (bit 1.4) ............................................................................................ 60
Auto-Negotiation Ability (bit 1.3) ............................................................................ 60
Link Status (bit 1.2) ................................................................................................ 60
Jabber Detect (bit 1.1) ........................................................................................... 61
Extended Capability (bit 1.0) .................................................................................. 61
Register 2: PHY Identifier Register ........................................................................ 62
ICS1893BF, Rev. C, 9/29/05
Copyright © 2005, Integrated Circuit Systems, Inc.
All rights reserved.
4
September, 2005
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
