ICSSSTV16857C
V
TT
R
L
=50Ω
From Output
Under Test
Test Point
C
L
= 30 pF
(see Note 1)
Load Circuit
LVCMOS
RESET#
Input
t
inact
I
DD
(see note 2)
V
DDQ
V
DDQ
/2
V
DDQ
/2
V
I(pp)
0V
t
act
90% I
DDH
10%
Voltage and Current Waveforms
Inputs Active and Inactive Times
t
w
V
IH
I
DDL
Output
Timing
Input
t
PHL
V
TT
V
TT
V
ICR
V
ICR
t
PHL
V
OH
V
OL
Voltage Waveforms - Propagation Delay Times
Input
V
REF
V
REF
V
IL
LVCMOS
RESET#
Input
V
IH
V
DD
/2
t
PHL
V
IL
Voltage Waveforms - Pulse Duration
V
I(pp)
Timing
Input
t
S
Input
V
REF
V
ICR
Output
V
TT
V
IH
V
REF
V
IL
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
V
OL
V
OH
t
h
Figure 1 - Parameter Measurement Information (V
DDQ
= 2.5V ±0.2V)
Notes:
1. CL incluces probe and jig capacitance.
2. I
DD
tested with clock and data inputs held at V
DDQ
or GND, and I
O
= 0 mA.
3. All input pulses are supplied by generators having the following characteristics: PRR @10 MHz,
Zo=50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. V
TT
= V
REF
= V
DDQ
/2
6. V
IH
= V
REF
+ 310mV (AC voltage levels) for differential inputs. V
IH
= V
DDQ
for LVCMOS input.
7. V
IL
= V
REF
- 310mV (AC voltage levels) for differential inputs. V
IL
= GND for LVCMOS input.
8. t
PLH
and t
PHL
are the same as t
pd
0002F—10/25/02
6
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
