ICS1527 Data Sheet
Section 3 Register map summary
Section 3
Word
Address
00h
Register map summary
Reset
Value
1
0
Name
Input
Control
Access
R/W
Bit Name
CPen
VSYNC_Pol
Bit #
0
1
Description
Charge Pump Enable
0=External Enable via VSYNC, 1=Always Enabled
VSYNC Polarity (Charge Pump Enable)
Requires 00h:0=0
0=Coast (charge pump disabled) while VSYNC low,
1=Coast (charge pump disabled) while VSYNC high
HSYNC Polarity
0=Rising Edge, 1=Falling Edge
External Feedback Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Select
0=Internal Feedback, 1=External
Reserved
Enable PLL Lock Status Output
0=Disable, 1=Enable
Reserved
HSYNC_Pol
Fbk_Pol
Fbk_Sel
Reserved
EnPLS
Reserved
2
3
4
5
6
7
0
0
0
0
1
0
01h
Loop
Control
*
R/W
ICP0-2
0-2
ICP (Charge Pump Current)
Bit 2,1,0 = {000 =1
µA,
001 = 2
µA,
010 = 4
µA...
110 = 64
µA,
111 =
128
µA}.
Increasing the PF Detector Gain makes the loop respond
faster, raising the loop bandwidth. The typical value when using the
internal loop filter is 011.
Reserved
VCO Divider
Bit 5,4= {00 = ÷2, 01=÷4, 10=÷8, 11=÷16}
Reserved
Reserved
VCOD0-1
Reserved
3
4-5
6-7
02h
FdBk Div
0
*
R/W
FBD0-7
0-7
Feedback Divider LSBs (bits 0-7)
03h
FdBk Div
1
*
R/W
FBD8-11
0-3
Feedback Divider MSBs (bits 8-11)
Divider setting = 12 bit word + 8
Minimum 12 = 000000000100
Maximum 4103 =111111111111
Reserved
Reserved
4-7
04h
Reserved
Reserved
0-7
0
Reserved
05h
Schmitt-
trigger
*
R/W
Schmitt
control
Metal_Rev
0
1-7
1
0
Schmitt-trigger control
0=Schmitt-trigger, 1=No Schmitt-trigger
Metal Mask Revision Number
06h
Output
Enables
R/W
Reserved
OE
Reserved
0
1
2-7
0
0
0
Reserved
Output Enable for CLK, HSYNC_out, VSYNC_out
0=High Impedance (disabled), 1=Enabled
Reserved
MDS1527 G
5
Revision 110905
In te grated Circuit Systems, 525 Race Stre e t, Sa n Jose , CA 95 126, tel (408 ) 29 7-120 1
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