ICS1531 Data Sheet - Preliminary
Chapter 10 Timing Diagrams
10.3.3 One-Pixel-per-Clock Mode Timing
For 1-pixel-per-clock mode, Reg 30:6 must be set to ‘1’. Table 10-6 lists time measures for this mode, and
Figure 10-5 shows timing characteristics.
Note: For the 1-pixel-per-clock mode, the ‘B’ channel data outputs are always at ground level.
Table 10-6. Timing for 1-Pixel-per-Clock Mode
Time
Timing Description
Min
Typ
Max Units
Period
Tp, Td CLK Period, CLK Duty Cycle
–
–
–
0
See Table 10-3.
t1 = Tp
TBD
–
–
ns
ns
ns
ns
t1
t2
t3
ACDRCLK Period
ADCRCLK Fall Time to ADCSYNC Rise Time
Digital Data Transition
–
2.0
2.5
Figure 10-7. AC Timing for 1-Pixel-per-Clock Mode
P+1
P+4
Analog Data In:
ARED
P
P+3
AGRN
ABLUE
P+2
P+5
Tp, Td
CLK
t1
ADCRCLK
t2
ADCSYNC
t3
‘A’ Channel Digital
Data Output
P-6
P-5
P-4
P-3
P-2
P-1
P
‘B’ Channel Digital
Data Output
ICS1531 Rev N 12/1/99
December, 1999
Copyright © 1999, Integrated Circuit Systems, Inc.
All rights reserved.
69
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
