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ICS1531 参数 Datasheet PDF下载

ICS1531图片预览
型号: ICS1531
PDF下载: 下载PDF文件 查看货源
内容描述: 888位MSPS A / D转换器与行同步时钟发生器 [Triple 8-bit MSPS A/D Converters with Line-Locked Clock Generator]
分类和应用: 转换器时钟发生器
文件页数/大小: 76 页 / 525 K
品牌: ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
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ICS1531 Data Sheet - Preliminary  
Chapter 10 Timing Diagrams  
Chapter 10 Timing Diagrams  
10.1 Industry-Standard 2-Wire Serial Bus Timing Diagrams  
10.1.1 Start and Stop Conditions  
Figure 10-1 shows in general terms how start and stop conditions work when transferring bits on an  
industry-standard 2-wire serial bus. All bus transactions begin with a start and end with a stop.  
To start a bus transfer (1), the clock signal from a master device (typically a microcontroller) is allowed to  
float high while the data signal driven by the master device transitions from high to low.  
The bytes transfer (2) from the master device to/from the ICS1531. (For details, see Section 10.1.2,  
“Transfer of Data Bytes”.)  
To stop a bus transfer (3), while the clock signal is high, the data signal transitions from low to high.  
Figure 10-1. Start and Stop Conditions  
Star  
(1)  
Byte Transfer  
(2)  
Stop  
(3)  
Clock from  
Master Device  
Data Signal  
ICS1531 Rev N 12/1/99  
December, 1999  
Copyright © 1999, Integrated Circuit Systems, Inc.  
All rights reserved.  
63  
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