ICS1526 Preliminary Data Sheet
Word
Address
07h
Reset
Value
0
Section 3 Register map summary
Name
Osc_Div
Access
R/W
Bit Name
Osc_Div 0-6
Bit #
0-6
Description
Osc Divider modulus
Minimum 3 =0000001 binary, Maximum 129 = 1111111 binary
Divider setting = 7-bit word + 2
Input Select
0=HSYNC Input, 1=OSC Input
OSC input clock must be present to select OSC input
In-Sel
7
0
08h
Reset
Write
PLL
0-7
x
Writing 5Ah resets PLL and commits values written to word
addresses 01h-03h and 05h
09-0Fh
Reserved
Read
Reserved
0-7
Reserved
10h
Chip Ver
Read
Reserved
0-7
Reserved
11h
Chip Rev
Read
Chip Rev
0-7
01
Reserved
12h
Rd_Reg
Read
Reserved
PLL_Lock
Reserved
0
1
2-7
N/A
N/A
0
Reserved
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
*. Written values to these registers do not take effect immediately, but require a commit via register 08h
MDS 1526 I
6
Revision 020304
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