ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 2
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
Pin Descriptions
TYPE
POWER
POWER
IN/OUT
IN
IN
IN
IN
IN
IN
POWER
POWER
IN
IN
DESCRIPTION
Digital supply
Digital ground
Serial data
Serial clock
Charge pump enable
External feedback in
Horizontal sync
External filter
External filter return
Analog supply
Analog ground
Oscillator
I
2
C address
I
2
C-bus Data
I
2
C-bus Clock
Enables\Disables the charge pump
External feedback divider input
Clock input to PLL
External loop filter
External loop filter return
3.3 V for analog circuitry
Ground for analog circuitry
Input from oscillator or other high
frequency input
Chip I
2
C address select
Low = 4Dh read, 4Ch write
High = 4Fh read, 4Eh write
REF (Schmitt conditioned HSYNC) or
PLL lock output
Output selectable between a 4 clock
wide, active high HSYNC-like output,
and a Schmitt-trigger filtered HSYNC
Output driver for half speed clock
Output driver for full speed clock
3.3 V to output drivers
Ground for output drivers
PECL driver for full-speed clock
PECL driver for half-speed clock
Reference current for PECL outputs
1&2
1
1
1
1
1
COMMENTS
3.3 V to digital sections
Notes
PIN NAME
VDDD
VSSD
SDA
SCL
COAST
EXTFB
HSYNC
EXTFIL
XFILRET
VDDA
VSSA
OSC
I
2
CADR
14
15
LOCK/REF
FUNC
SSTL
_
3 OUT
SSTL
_
3 OUT
Lock / Reference
Function output
16
17
18
19
20
21
22
23
24
CLK/2
CLK
VDDQ
VSSQ
CLK–
CLK+
CLK/2–
CLK/2+
IREF
SSTL
_
3 OUT
SSTL
_
3 OUT
POWER
POWER
OD OUT
OD OUT
IN
Pixel clock/2 output
Pixel clock output
Output driver supply
Output driver ground
Pixel clock outputs
Pixel clock/2 outputs
Reference current
Note 1: These LVTTL inputs are 5 V-tolerant.
Note 2: Connect to ground if unused.
MDS 1523 Y
Integrated Circuit Systems
4
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 110905
www.icst.com
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
