ICS1523
Video Clock Synthesizer with I
2
C Programmable Delay
Section 4
Reg.
Index
0x0
Register Set Summary
Reset
Value
1
0
0
0
0
0
1
0
Name
Input
Control
Access
R/W
Bit Name
CPen
CP_Pol
Ref_Pol
Fbk_Pol
Fbk_Sel
Func_Sel
EnPLS
EnRef
Bit #
0
1
2
3
4
5
6
7
Description
Charge Pump Enable
0=External Enable via COAST Pin, 1=Always Enabled
COAST Pin Charge Pump Enable Polarity
0=Active High, 1=Active Low
External Reference Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Polarity
0=Positive Edge, 1=Negative Edge
External Feedback Select
0=Internal Feedback, 1=External
FUNC Pin Output Select (DPA delayed)
0=Recovered HSYNC, 1=Input HSYNC
Enable PLL Lock/Ref Status Output
0=Disable 1=Enable
1=Enable Ref to Lock/Ref Output
Note
3
3
4
4
0x1
Loop
Control
R/W
ICP0-2
0-2
0
ICP (Charge Pump Current)
Bit 2,1,0=(000 =1 uA, 001 = 2 uA, 010 = 4 uA, 011 = 8 uA,
100 = 16 uA, 101 = 32 uA, 110 = 64 uA, 111 = 128 uA
Reserved
VCO Divider Bit 5,4 =(00 = ÷2, 01=÷4, 10=÷8, 11=÷16)
Reserved
1, 6
Reserved
VCOD0-1
Reserved
3
4-5
6-7
0
0
0
1, 7
0x2
FdBk Div 0
R/W
FBD0-7
0-7
FF
Feedback Divider LSBs (Bit 7, 6, 5, 4, 3, 2, 1, 0)
Actual # of clocks = Programmed value + 8
1
0x3
FdBk Div 1
R/W
FBD8-11
Reserved
0-3
4-7
F
0
Feedback Divider MSBs (Bit 11, 10, 9, 8)
Reserved
1
0x4
DPA Offset
R/W
DPA_OS0-5
Reserved
Fil_Sel
0-5
6
7
0
0
0
Dynamic Phase Aligner Offset
Bit 5, 4, 3, 2, 1, 0 = (MUST be < total # of DPA elements)
Reserved
Loop Filter Select (0=External, 1=Internal)
8
6
0x5
DPA
Control
R/W
DPA_Res0-1
Metal_Rev
0-1
2-7
3
0
DPA Resolution, Total # of delay elements
Bit 1, 0 = (00 = 16, 01 = 32, 10 = Reserved, 11 = 64)
Metal Mask Revision Number
2, 8
Note 1: Double-buffered register. Working registers are loaded during software PLL reset. See 0x8.
Note 2: Double-buffered register. Working registers are loaded during software DPA reset. See 0x8.
Notes 3~8: See
MDS 1523 Y
Integrated Circuit Systems
6
525 Race Street, San Jose, CA 95126
tel (408) 297-1201
Revision 110905
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