IC61LV6432
READ/WRITE CYCLE TIMING: PIPELINE
t
KC
CLK
ADSP
ADSC
t
KH
tKL
ADSP is blocked by CE1 inactive
t
SS
tSH
t
SS
tSH
ADV
t
AS
tAH
A15-A0
RD1
WR1
RD2
RD3
t
t
WS
WS
t
t
WH
GW
BWE
WH
t
WS
tWH
WR1
BW4-BW1
t
CES
tCEH
CE1 Masks ADSP
CE1
CE2
CE3
t
t
CES
CES
t
t
CEH
CEH
CE2 and CE3 only sampled with ADSP or ADSC
Unselected with CE3
t
OEHZ
t
OEQ
OE
t
KQX
t
OEQX
t
OELZ
High-Z
High-Z
DATAOUT
2a
2b
2c
2d
1a
t
KQLZ
t
KQHZ
t
KQX
KQHZ
t
KQ
t
1a
DATAIN
t
DS
tDH
Single Write
Burst Read
Single Read
Unselected
16
Integrated Circuit Solution Inc.
SSR005-0A 002/02/2004