IC42S32200
IC42S32200L
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
COMMAND
DQ’s
NOP
READ A
NOP
NOP
NOP
NOP
WRITE B
DINB
NOP
NOP
DOUT A
DINB
DINB
2
0
1
Must be Hi-Z before
the Write Command
: "H" or "L"
Read to Write Interval (Burst Length = 4,CAS#Latency =3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
1 Clk Interval
DQM
BANKA
ACTIVAT E
READ A
COMMAND
WRITEA
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
tCK2, DQs
DIN A
0
DIN A
DIN A
DIN A
3
1
2
: "H" or "L"
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DQM
NOP
READ A
WRITEB
DIN B
COMMAND
NOP
NOP
NOP
NOP
NOP
NOP
CAS# latency=2
DIN B
DIN B
DIN B
3
t
, DQ’s
tCK2, DQs
0
1
2
CK2
: "H" or "L"
Read to Write Interval (Burst Length = 4,CAS#Latency =2)
A read burst without the auto precharge function may be interrupted by a BankPrecharge/
PrechargeAll command to the same bank.The following figure shows the optimum time that
BankPrecharge/PrechargeAll command is issued in different CAS#latency.
10
Integrated Circuit Solution Inc.
DR036-0D 02/04/2005
ICSI [ INTEGRATED CIRCUIT SOLUTION INC ]
