AV9172
Pin Configuration
Functionality Table for AV9172-01
CLKIN input frequency range 10 to 50 MHz.
EN2
0
0
1
1
INV#
0
1
0
1
Q0
1X
1X
1X
1X
Q1
1X#
1X
1X#
1X
Q2
2X
2X
2X
2X
Q3
2X
2X
2X
2X
Q4
2X
2X
∅
1
∅
1
Q5
2X
2X
∅
2
∅
2
16-Pin SOIC or 16-Pin PDIP
Notes:
1. 1X designates that the output is a replica of CLKIN.
2. 2X designates that the output is twice the frequency of
CLKIN, and in phase.
3. 1X# means that the output is at the same frequency and
180°C out of phase (inverted) from CLKIN.
4. Ø1 will produce a ¼ duty cycle clock of CLKIN.
5. Ø2 will produce a ¼ duty cycle clock delayed 180° from
CLKIN.
Pin Description for AV9172-01
PIN NUMBER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIN NAME
GND
GND
INV#
EN
FBIN
CLKIN
VDD
VDD
GND
Q0
Q1
Q2
Q3
Q4
Q5
VDD
TYPE
-
-
Input
Input
Input
Input
-
-
-
Output
Output
Output
Output
Output
Output
-
DESCRIPTION
GROUND.
GROUND.
INV# Inverts Q1 when low. (-01 [divisor select -03, -07])
EN converts Q4 and Q5 to phase clocks when high.
FEEDBACK INPUT from output Q0.
INPUT for reference clock.
Power supply (+5V).
Power supply (+5V).
GROUND.
Q0 phase and frequency same as input (1X). Feed back to pin 5.
Q1
Q2
Q3
Q4
Q5
is a 1x clock in phase or 180° out of phase with input.
twice the frequency of Q0 (2x).
twice the frequency of Q0 (2x).
is either a 2X clock or a two-phase clock - see configuration table.
is either a 2X clock or a two-phase clock - see configuration table.
Power supply (+5V).
2
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