AV9172
Pin Configuration
Functionality Table for AV9172-03
CLKIN Input Frequency=X, input range is 10 to 50 MHz.
EN2
0
1
0
1
INV#
0
0
1
1
Q0
2X
2X
2X
2X
Q1
2X
2X
2X
2X
Q2
2X
2X
2X
2X
Q3
2X
2X
1X
1X
Q4
2X
2X
1X
1X
Q5
2X
1X
2X
1X
Example Table for AV9172-03
16-Pin SOIC or 16-Pin PDIP
(33 MHz input, all frequencies in MHz.)
EN2
0
1
0
1
INV#
0
0
1
1
Q0
66
66
66
66
Q1
66
66
66
66
Q2
66
66
66
66
Q3
66
66
33
33
Q4
66
66
33
33
Q5
66
33
66
33
Timing Diagram for AV9172-03
Note: The phase alignment between the 1X clock outputs and
reference clocks input will be either at a 0 or 180 degrees
offset if the 2X clock is used as the feedback signal (con-
nected to the FBIN pin). Which relationship occurs is totally
random and has the potential to change any time the device has
its VDD supply cycled off or the devices input clock
removed.
4
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