Integrated
Circuit
Systems, Inc.
AV9170
Clock Synchronizer and Multiplier
General Description
The
AV9170
generates an output clock which is synchronized
to a given continuous input clock with zero delay (±1ns at 5V
V
DD
). Using ICSs proprietary phase-locked loop (PLL) ana-
log CMOS technology, the
AV9170
is useful for regenerating
clocks in high speed systems where skew is a major concern.
By the use of the two select pins, multiples or divisions of the
input clock can be generated with zero delay (see Tables 2 and
3). The standard versions produce two outputs, where CLK2
is always a divide by two version of CLK1.
The
AV9170
is also useful to recover poor duty cycle clocks.
A 50 MHz signal with a 20/80% duty cycle, for example, can
be regenerated to the 48/52% typical of the part.
The
AV9170
allows the user to control the PLL feedback,
making it possible, with an additional 74F240 octal buffer (or
other such device that offers controlled skew outputs), to
synchronize up to 8 output clocks with zero delay compared to
the input (see Figure 1). Application notes for the
AV9170
are
available. Please consult ICS.
Features
On-chip Phase-Locked Loop for clocks synchronization
Synchronizes frequencies up to 107 MHz
(output) @ 5.0V
±1ns skew (max) between input & output clocks @ 5.0V
Can recover poor duty cycle clocks
CLK1 to CLK2 skew controlled to within ±1ns @ 5.0V
3.0 - 5.5V supply range
Low power CMOS technology
Small 8-pin DIP or SOIC package
On chip loop filter
AV9170-01, -04
for output clocks 20-107 MHz @ 5.0V,
20 - 66.7 MHz @ 3.3V
AV9170-02, -05
for output clocks 5-26.75 MHz @ 5.0V,
5 - 16.7 MHz @ 3.3V
Block Diagram
AV 9170 Rev E 9/24/99
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
