AV9108
Pin Configuration
FS0
GND
X1/ICLK
X2
1
2
3
4
8
7
6
5
REFCLK
VDD
CLK1
FS1
FS1
FS2
FS3
AGND
GND
PD
X1/ICLK
1
2
3
4
5
6
7
14
13
12
11
10
9
8
FS0
REFCLK
VDD
CLK1
OE (CLK1)
OE (REFCLK)
X2
AV9108-05/-10
8-Pin DIP, SOIC
AV9108-03/-11
14-Pin DIP, SOIC
Pin Descriptions for
AV9108-03, AV9108-05 and AV9108-10
PIN NUMBER
-05/-10/-13
1
5
-03
14
1
2
3
4
5
6
7
8
9
10
11
12
13
PIN
NAME
FS0
FS1
FS2
FS3
AGND
GMD
PD
X1/ICLK
X2
OE(REFCLK)
OE(CLK1)
CLK1
VDD
REFCLK
TYPE
Input
Input
Input
Input
-
-
Input
Input
Output
Input
Input
Output
-
Output
DESCRIPTION
Frequency Select 0 for CLK1 (-03 has pull-up).
Frequency Select 1 for CLK1 (-03 has pull-up).
Frequency Select 2 for CLK1 (-03 has pull-up).
Frequency Select 3 for CLK1 (-03 has pull-up).
Analog GROUND.
Digital GROUND.
POWER-DOWN. Shuts off chip when low. Internal pull-up.
CRYSTAL OUTPUT or INPUT CLOCK frequency. Typically 14.318 MHz
system clock.
CRYSTAL OUTPUT (No Connect when clock used.).
OUTPUT ENABLE. Tristates REFCLK when low. Pull-up.
OUTPUT ENABLE. Tristates CLK1 when low. Pull-up.
CLOCK1 Output (see decoding tables).
Digital power supply (+3V DC).
REFERENCE CLOCK output. Produces a buffered version of the input clock or
crystal frequency (typically 14.318 MHz).
2
3
4
6
7
8
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
