ICS95V857
Pin Descriptions
PIN NAME
VDD
GND
AVDD
AGND
CLKT(9:0)
CLKC(9:0)
CLK_INC
CLK_INT
FB_OUTC
TYPE
PWR
PWR
PWR
PWR
OUT
OUT
IN
IN
OUT
Power supply, 2.5V
Ground
Analog power supply, 2.5V
A n a l o g gr o u n d
"Tr ue" Clock of differential pair outputs
"Complementar y" clocks of differential pair outputs
"Complementar y" reference clock input
"True" reference clock input
"Complementar y" Feedback output, dedicated for external feedback. It
switches at the same frequency as the CLK. This output must be wired
to FB_INC
"True" " Feedback output, dedicated for external feedback. It switches
at the same frequency as the CLK. This output must be wired to
FB_INT
"True" Feedback input, provides feedback signal to the internal PLL for
synchronization with CLK_INT to eliminate phase error
"Complementar y" Feedback input, provides signal to the internal PLL
for synchronization with CLK_INC to eliminate phase error
Power Down. LVCMOS input
DESCRIPTION
FB_OUTT
FB_INT
FB_INC
PD#
OUT
IN
IN
IN
This PLL Clock Buffer is designed for a V
DD
of 2.5V, an AV
DD
of 2.5V and differential data input and output levels.
The
ICS95V857
is a zero delay buffer that distributes a differential clock input pair (CLK_INC, CLK_INT) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT,
FB_OUTC). The clock outputs are controlled by the input clocks (CLK_INC, CLK_INT), the feedback clocks (FB_INT,
FB_INC), the 2.5-V LVCMOS input (PD#) and the Analog Power input (AV
DD
). When input (PD#) is low while power is
applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter
a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers,
will detect the low frequency condition and perform the same low power features as when the (PD#) input is low. When
the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and
outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input
clock pair (CLK_INC, CLK_INT).
The PLL to the
ICS95V857
clock driver uses the input clocks (CLK_INC, CLK_INT) and the feedback clocks (FB_INT,
FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The
ICS95V857
is also able to track Spread Spectrum Clock (SSC) for reduced EMI.
The
ICS95V857
is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class
A+ for registered DDR clock drivers.
0674U—01/27/09
3
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