ICS95V857
Timing Requirements
T
A
= 0 - 85°C; Supply Voltage A
VDD
, V
DD
= 2.5 V +/- 0.2V (unless otherwise stated)
CONDITIONS
PARAMETER
SYMBOL
MIN
MAX
Max clock frequency
Application Frequency
Range
Input clock duty cycle
CLK stabilization
freq
op
freq
App
d
tin
T
STAB
2.5V+0.2V @ 25
o
C
2.5V+0.2V @ 25
o
C
45
95
40
233
220
60
15
UNITS
MHz
MHz
%
µs
Switching Characteristics (see note 3)
PARAMETER
Low-to high level
propagation delay time
High-to low level propagation
delay time
Output enable time
Output disable time
Period jitter
Half-period jitter
Input clock slew rate
Output clock slew rate
SYMBOL
t
PLH1
t
PLL1
t
EN
tdis
T
jit (per)
t(jit_hper)
t
sl(i)
t
sl(o)
T
cyc
-T
cyc
CONDITION
CLK_IN to any output
CLK_IN to any output
PD# to any output
PD# to any output
100MHz to 200MHz
100MHz to 200MHz
MIN
TYP
3.5
3.5
3
3
-30
-75
1
1
-50
-50
30
75
4
2
50
50
40
MAX
UNITS
ns
ns
ns
ns
ps
ps
V/ns
V/ns
ps
ps
ps
100MHz to 200MHz
Cycle to Cycle Jitter
1
4
Static Phase Offset
0
t
(static phase offset)
Output to Output Skew
T
skew
Notes:
1. Refers to transition on noninverting output in PLL bypass mode.
2. While the pulse skew is almost constant over frequency, the duty cycle error
increases at higher frequencies. This is due to the formula: duty cycle=t
wH
/t
c
, where
the cycle (t
c
) decreases as the frequency goes up.
3. Switching characteristics guaranteed for application frequency range.
4. Static phase offset shifted by design.
0674U—01/27/09
6
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
