PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS83904-02
L
OW
S
KEW
, 1-
TO
-4
C
RYSTAL
-
TO
-LVCMOS/LVTTL F
ANOUT
B
UFFER
Test Conditions
w/External XTAL
Minimum
10
200
1.8
TBD
TBD
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
0.16
420
50
10
8
Typical
Maximum
40
Units
MHz
MH z
ns
ps
ps
ps
ps
%
ns
ns
T
ABLE
6A. AC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
Output Frequency
t
sk(o)
t
sk(pp)
t
jit(Ø)
t
R
/ t
F
odc
t
EN
Output Disable Time; NOTE 5
t
DIS
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
T
ABLE
6B. AC C
HARACTERISTICS
,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= 0°C
TO
70°C
Symbol Parameter
f
MAX
tp
LH
w/External CLK
Propagation Delay, Low-to-High;
NOTE 1
Output Skew; NOTE 2
Par t-to-Par t Skew; NOTE 2, 3
RMS Phase Jitter, Random;
NOTE 2, 4
Output Rise/Fall Time
Output Duty Cycle
Output Enable Time; NOTE 5
25MHz, Integration Range:
100Hz - 1MHz
20% to 80%
Output Frequency
w/External XTAL
Test Conditions
Minimum
10
200
2
TBD
TBD
0.16
440
50
10
8
Typical
Maximum
40
Units
MHz
MH z
ns
ps
ps
ps
ps
%
ns
ns
t
sk(o)
t
sk(pp)
t
jit(Ø)
t
R
/ t
F
odc
t
EN
Output Disable Time; NOTE 5
t
DIS
NOTE 1: Measured from V
DD
/2 of the input to V
DDO
/2 of the output.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V
DDO
/2.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
83904AG-02
www.icst.com/products/hiperclocks.html
REV. A JULY 8, 2005
5
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
