Philips Semiconductors
Product specification
Dual non-inverting Schmitt-trigger with
5 V tolerant input
FEATURES
•
Wide supply voltage range from 1.65 to 5.5 V
•
5 V tolerant input/output for interfacing with 5 V logic
•
High noise immunity
•
Complies with JEDEC standard:
– JESD8-7 (1.65 to 1.95 V)
– JESD8-5 (2.3 to 2.7 V)
– JESD8B/JESD36 (2.7 to 3.6 V).
•
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V.
• ±24
mA output drive (V
CC
= 3.0 V)
•
CMOS low power consumption
•
Latch-up performance exceeds 250 mA
•
Direct interface with TTL levels
•
SOT363 and SOT457 package
•
Specified from
−40
to +125
°C.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C.
SYMBOL
t
PHL
/t
PLH
PARAMETER
CONDITIONS
V
CC
= 2.5 V; C
L
= 30 pF; R
L
= 500
Ω
V
CC
= 2.7 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 3.3 V; C
L
= 50 pF; R
L
= 500
Ω
V
CC
= 5.0 V; C
L
= 50 pF; R
L
= 500
Ω
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW).
P
D
= C
PD
×
V
CC2
×
f
i
×
N +
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts;
N = total load switching outputs;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs.
2. The condition is V
I
= GND to V
CC
.
input capacitance
power dissipation capacitance per buffer V
CC
= 3.3 V; notes 1 and 2
DESCRIPTION
APPLICATIONS
74LVC2G17
•
Wave and pulse shapers for highly noisy environments.
The 74LVC2G17 is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. These
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
This device is fully specified for partial power-down
applications using I
off
. The I
off
circuitry disables the output,
preventing the damaging back flow current through the
device when it is powered down.
The 74LVC2G17 provides two non-inverting buffers with
Schmitt-trigger action. It is capable of transforming slowly
changing input signals into sharply defined, jitter-free
output signals.
TYPICAL
5.6
3.7
3.8
3.6
2.7
3.5
16.3
ns
ns
ns
ns
ns
UNIT
propagation delay inputs nA to output nY V
CC
= 1.8 V; C
L
= 30 pF; R
L
= 1 kΩ
pF
pF
2003 Aug 13
2
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
