PE4270
Product Specification
Figure 3. Pin Configuration
V
DD
GND
RF1
1
2
3
Exposed
Solder Pad
(bottom side)
Table 4. DC Electrical Specifications
Parameter
Min
2.7
Typ
3.0
8
Max
3.3
20
5
0.3xV
DD
Unit
V
µA
V
V
6
5
4
RF2
GND
V
DD
Power Supply
I
DD
Power Supply Current
(V
DD
= 3V, V
CTRL
= 3V)
Control Voltage High
Control Voltage Low
0.7xV
DD
0
CTRL
Table 5. Control Logic Truth Table
Control Voltage (CTRL)
Signal Path (RF1 to RF2)
ON
OFF
High
1
Table 2. Pin Descriptions
Pin
No.
1
2
3
4
5
6
Pin Name
V
DD
GND
RF1
CTRL
GND
RF2
Description
Nominal 3 V supply connection.
Ground connection.
2
RF port.
1
CMOS or TTL logic level:
High = RF1 to RF2 signal path
Low = RF1 isolated from RF2
Ground connection.
3
RF port.
1
Low
Notes: 1.
CTRL accepts both CMOS and TTL voltage leads.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS™
devices are immune to latch-up.
Unit
V
V
°C
°C
dBm
V
Notes: 1. Both RF pins must be held at 0 V
DC
or require external DC
blocking capacitors
2. The exposed pad must be soldered to the ground plane for
proper switch performance.
Table 3. Absolute Maximum Ratings
Symbol
V
DD
V
I
T
ST
T
OP
P
IN
V
ESD
Parameter/Condition
Power supply voltage
Voltage on CTRL input
Storage temperature
Operating temperature
Input power (50
Ω),
CTRL=1/CTRL=0
ESD voltage
(Human Body Model)
Min
-0.3
-0.3
-65
-40
Max
4.0
5.5
150
85
33/24
500
Device Description
The
PE4270
high isolation SPST CATV Switch is
designed to support CATV applications such as
premise disconnect of a CATV signal path. This
function is typically performed by bulky and
expensive mechanical relays. The high isolation
characteristics, high compression point, and
integrated 75-ohm terminations make the
PE4270
an ideal, cost effective and manufacturable
product of choice.
The control logic input pin (CTRL) is typically
driven by a 3-volt CMOS logic level signal, and
has a threshold of 50% of V
DD
. For flexibility to
support systems that have 5-volt control logic
drivers, the control logic input has been designed
to handle a 5-volt logic HIGH signal. (A minimal
current will be sourced out of the V
DD
pin when the
control logic input voltage level exceeds V
DD
.)
Document No. 70-0148-03
│
UltraCMOS™ RFIC Solutions
Absolute Maximum Ratings are those values
listed in the above table. Exceeding these values
may cause permanent device damage.
Functional operation should be restricted to the
limits in the DC Electrical Specifications table.
Exposure to absolute maximum ratings for
extended periods may affect device reliability.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 8
ICS [ INTEGRATED CIRCUIT SYSTEMS ]
